<P><SPAN class=h1>The IEEE VLSI Test Symposium (VTS) explores emerging trends and novel concepts in testing, and verification / validation of microelectronic circuits and systems.</SPAN> <BR class=short>The VTS Program Committee invites original, unpublished paper submissions for VTS 2008. Paper submissions should be complete manuscripts, up to eight pages (inclusive of figures, tables, and bibliography) in a standard IEEE two–column format; papers exceeding the page limit will be returned without review. Authors should clearly explain the significance of the work, highlight novel features, and describe its current status.<BR><B>Keywords:</B></P> <P> <TABLE> <TBODY> <TR> <TD vAlign=top> <LI>Analog, M–S & RF Test <LI>Automatic Test Generation <LI>ATE Architecture & SW <LI>Board & System Test <LI>Built–In Self–Test (BIST) <LI>Current Based Test <LI>Defect Tolerance <LI>Delay & Performance Test <LI>Design for Testability (DFT) <LI>Design Verification/Validation <LI>Diagnosis and Debug <LI>Embedded System Test <LI>Embedded Test Methods <LI>Fault Modeling and Simulation <LI>Infrastructure IP <LI>MEMS Test <LI>Memory Test and Repair </LI></TD> <TD vAlign=top> <LI>Microprocessor Test <LI>Multi–Chip Module Test <LI>Nanometer Technologies Test <LI>On–Line Test <LI>Power Issues in Test <LI>Self–Repair & Fault Tolerance <LI>System–on–Chip (SOC) Test <LI>System–in–Package Test <LI>Test Resource Partitioning <LI>Thermal Test <LI>Test Data Compression <LI>Test of High–Speed I/O <LI>Test Quality and Reliability <LI>Test Resource Partitioning <LI>Transients and Soft Errors <LI>Yield Analysis & Optimization</LI></TD></TR></TBODY></TABLE></P>
Abbrevation
VTS
City
San Diego
Country
United States
Deadline Paper
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