<P>Dramatic embedded systems volumes and associated market segments force a reevaluation of the best way to satisfy the possibly conflicting demands placed on processor designs. Domain–specific embedded processors, such as network, automotive, cellular and others, present interesting architectural refinements, albeit at the cost of splintering the embedded processor market. Reprogrammable and/or reconfigurable embedded processors provide an alternative approach, capable of delivering single, fixed–silicon architectures, thus amortizing design and manufacturing costs across large volumes, yet necessitating an answer to the challenge of effective customization of embedded processors. The symposium explores (micro)architectural design approaches and trade–offs and compiler technologies, for both domain–specific and customizable embedded processors. </P><B>Keywords:</B> <LI>Domain–specific processors (Network, multimedia, etc.) <LI>Application–specific hardware accelerators <LI>Microarchitectural customization techniques <LI>(Re)configurable processor architectures <LI>Dynamically reconfigurable processors (Microarchitectural, Coarse–grained, FPGA, etc.) <LI>Application–specific processors in System–on–a–chip (SOC) <LI>Application–specific customizations for low–power <LI>Compiler technology targeting customizable processors <LI>Architectural exploration and hardware software codesign <LI>Application specific MPSoC <LI>Design Automation for NoCs <LI>OS and Middleware support for application specific processors </LI>
Abbrevation
SASP
City
Anaheim
Country
United States
Deadline Paper
Start Date
End Date
Abstract