<DIV class=para5><SPAN class=text9><FONT face=Times>The decline in the growth of single–processor performance, the growing concerns with energy consumption, and the still exponential increase in transistors per chip as per Moore′s law, will open the scene for single–chip processors with a substantial amount of parallelism to meet the demands for extremely high performance, reliability, and controlable power consumption in all areas of computing. The major challenge for the coming years will be the design of architectures supporting manageable programming abstractions to allow the mainstream programmer to take advantage of the processing power promised by the technological developments. </FONT></SPAN></DIV> <DIV class=para5><SPAN class=text9><BR><FONT face=Times></FONT></SPAN></DIV> <DIV class=para5><SPAN class=text9><FONT face=Times>HPPC, the second workshop in the series, co–located with the EuroPar conference, is *the* workshop dedicated to addressing all aspects of highly parallel processing on a chip, be it in existing or emerging multi–core designs, or in bold, new proposals for architectures, programming models, languages and libraries for managing and exploiting massive levels of parallelism on a chip. Particular emphasis is on the interaction between hardware, architecture (processors, on–chip networks, cache and memory system), programming models and languages, and algorithms as well as applications in need of significant amounts of single–chip parallelism. The workshop will be conducted in an informal atmosphere, stressing interaction and discussion between presenters and audience. </FONT></SPAN></DIV> <P><B>Keywords:</B></P> <DIV class=para5><SPAN class=text9><FONT face=Times>° hardware techniques (e.g. power saving, clocking, fault–tolerance) </FONT></SPAN></DIV> <DIV class=para5><SPAN class=text9><FONT face=Times>° processor core architectures (homogeneous and heterogeneous) </FONT></SPAN></DIV> <DIV class=para5><SPAN class=text9><FONT face=Times>° special purpose processors (accelerators) </FONT></SPAN></DIV> <DIV class=para5><SPAN class=text9><FONT face=Times>° on–chip memory and cache (or cache–less) organization, and interconnects </FONT></SPAN></DIV> <DIV class=para5><SPAN class=text9><FONT face=Times>° off–chip memory, I/O, and multi–core interconnects </FONT></SPAN></DIV> <DIV class=para5><SPAN class=text9><FONT face=Times>° overall system design (resource allocation and balancing) </FONT></SPAN></DIV> <DIV class=para5><SPAN class=text9><FONT face=Times>° programming models (e.g. PRAM, BSP, data parallel, vector, transactional), </FONT></SPAN></DIV> <DIV class=para5><SPAN class=text9><FONT face=Times>° languages and software libraries </FONT></SPAN></DIV> <DIV class=para5><SPAN class=text9><FONT face=Times>° implementation techniques (e.g. multi–threading, work–stealing) </FONT></SPAN></DIV> <DIV class=para5><SPAN class=text9><FONT face=Times>° support and performance tools, performance evaluation </FONT></SPAN></DIV> <DIV class=para5><SPAN class=text9><FONT face=Times>° parallel algorithms and applications </FONT></SPAN></DIV>
Abbrevation
HPPC
City
Las Palmas de Gran Canaria
Country
Spain
Deadline Paper
Start Date
End Date
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