Abbrevation
DFT
City
Cambridge
Country
United States
Deadline Paper
Start Date
End Date
Abstract

<DIV style=&#8243;TEXT&#8211;ALIGN: justify&#8243;> <DIV class=std style=&#8243;TEXT&#8211;ALIGN: justify&#8243;>DFT is an annual Symposium providing an open forum for presentations in the field of defect and fault tolerance in VLSI systems inclusive of emerging technologies&#046; One of the unique features of this symposium is to combine new academic research with state&#8211;of&#8211;the&#8211;art industrial data, necessary ingredients for significant advances in this field&#046; All aspects of design, manufacturing, test, reliability, and availability that are affected by defects during manufacturing and by faults during system operation are of interest&#046;<BR><B>Keywords:</B> </DIV> <DIV class=std style=&#8243;TEXT&#8211;ALIGN: justify&#8243;> <OL> <LI><SPAN style=&#8243;FONT&#8211;WEIGHT: bold&#8243;>Yield Analysis and Modeling </SPAN><BR>Defect/Fault analysis and models; statistical yield modeling; critical area and other metrics&#046; <LI><SPAN style=&#8243;FONT&#8211;WEIGHT: bold&#8243;>Repair, Restructuring and Reconfiguration</SPAN><BR>Repairable logic, reconfiguration, repair; reconfigurable circuit design; DFT for on&#8211;line operation&#046; <LI><SPAN style=&#8243;FONT&#8211;WEIGHT: bold&#8243;>Testing Techniques</SPAN><BR>Built&#8211;in self&#8211;test; delay fault modeling and diagnosis; testing for analog and mixed circuits; signal and clock integrity&#046; <LI><SPAN style=&#8243;FONT&#8211;WEIGHT: bold&#8243;>Error Detection, Correction, and Recovery</SPAN><BR>Self&#8211;testing and self&#8211;checking design; error&#8211;control coding; fault masking and avoidance; recovery schemes, space/time redundancy&#046; <LI><SPAN style=&#8243;FONT&#8211;WEIGHT: bold&#8243;>Defect and Fault Tolerance</SPAN><BR>Reliable circuit synthesis; radiation hardened/tolerant processes and design; transient/soft faults and errors&#046; <LI><SPAN style=&#8243;FONT&#8211;WEIGHT: bold&#8243;>Dependability Analysis and Validation</SPAN><BR>Fault injection techniques and environments; dependability characterization of IC and systems&#046; <LI><SPAN style=&#8243;FONT&#8211;WEIGHT: bold&#8243;>Emerging Technologies</SPAN><BR>DFT techniques for CNTs, QCA, DNA, RTDs, SETs, molecular devices and self&#8211;assembly&#046; <LI><SPAN style=&#8243;FONT&#8211;WEIGHT: bold&#8243;>Design For Testability in IC Design</SPAN><BR>FPGA, SoC, NoC, ASIC, microprocessors&#046; <LI><SPAN style=&#8243;FONT&#8211;WEIGHT: bold&#8243;>Totally Fail&#8211;Safe Design for Critical Applications</SPAN><BR>Methodologies and case study applications to automotive, railway, avionics, industrial control, biomedicine and space&#046;</LI></OL></DIV></DIV>