D43D System design for 3D silicon intergration Workshop, Grenoble, Frankreich

Abbrevation

WADS

Link

http://www.minatec-crossroads.com/uk/eve_workshop-d43d.htm

City

Grenoble

Country

France

Start Date

2008-06-27

End Date

2008-06-27

Abstract

3–D ICs enable dramatically improved performances at a much lower cost compared with new leading–edge sub 32 nm transistor fabrication. The success of these new ICs depends on the availability of new methodologies and skills that are required to achieve acceptable design quality and productivity. This workshop brings together key actors from the semiconductor, system houses and design industry to build a vision of the next step in 3D integrated ICs design. Keywords: <DIV class=″paragraph Free_Form″ style=″MARGIN–TOP: 0px; MARGIN–BOTTOM: 0px; PADDING–BOTTOM: 0pt; LINE–HEIGHT: 16px; TEXT–ALIGN: justify″><IMG height=8 src=″http://www.minatec–crossroads.com/img/taquet.gif&#…; width=25><IMG height=3 src=″http://www.minatec–crossroads.com/img/puce_small.g…; width=5> Applications requiring 3D <IMG height=8 src=″http://www.minatec–crossroads.com/img/taquet.gif&#…; width=25><IMG height=3 src=″http://www.minatec–crossroads.com/img/puce_small.g…; width=5> Interconnect architectures and thermal management for 3D ICs <IMG height=8 src=″http://www.minatec–crossroads.com/img/taquet.gif&#…; width=25><IMG height=3 src=″http://www.minatec–crossroads.com/img/puce_small.g…; width=5> Application partitioning floor planning for 3D architectures <IMG height=8 src=″http://www.minatec–crossroads.com/img/taquet.gif&#…; width=25><IMG height=3 src=″http://www.minatec–crossroads.com/img/puce_small.g…; width=5> Modeling characterization and testing for 3D ICs.</DIV>