<P>The eleventh annual IITC is sponsored by the IEEE Electron Devices Society as a premier conference for interconnect technology.</P> <P>The IITC provides a forum for professionals and researchers in semiconductor processing, advanced materials, equipment development, and interconnectg systems to present and discuss exciting new science and technology. Now in its second decade, the conference will include new subjects of interest such as Materials and Unit Processes, Manufacturing Issues and System in a Package.</P> <P><B>Keywords:</B> </P> <P>Materials and Unit Processes <UL> <LI>Dielectric materials (low k, high k, ARCs, etc.) and associated deposition processes (vapor deposition, CVD, spin–on, etc.) <LI>Metal deposition processes/equipment (PVD, CVD, ALD, electroplating, etc.) planarization processes for dielectrics and metals, equipment and metrology issues. Alternative planarization techniques <LI>Interconnect specific patterning processes (lithography, etch, etc.) including wet/dry strip and cleaning <LI>Novel or improved tools for metrology and characterization applicable to interconnect</LI></UL> <P></P> <P>Process Integration: <UL> <LI>Multilevel interconnect processes, clustered processes, novel interconnect structures, contact/via integration, metal barrier and materials interface issues, etc. <LI>Integration processes and issues specific to logic or memory <LI>Papers on novel non–volatile, interconnect embedded memories (PCM, resistive, etc.)</LI></UL> <P></P> <P>Process Modeling <UL> <LI>CMP, metal/dielectric deposition and etching processes, PVD, CVD, electroplating, etc.</LI></UL> <P></P> <P>Reliability <UL> <LI>Metal electromigration and stress voiding, dielectric integrity and mechanical stability, thermal effects, passivation issues, interconnect reliability prediction/modeling.</LI></UL> <P></P> <P>3D Processes and Integration <UL> <LI>Materials, process integration, 3D with memory, interactions with packaging, reliability</LI></UL> <P></P> <P>Interconnect Systems: <UL> <LI>Interconnect performance modeling and high frequency characterization <LI>Interconnect system integration, novel architectures and advanced interconnect concepts (optical, superconductors, etc.).</LI></UL> <P></P> <P>System in a Package <UL> <LI>Advanced packaging concepts (flip–chi, chip–on–chip, MCM, etc.) <LI>Novel IC interconnect – package architectures, interactions with Cu/low k, wafer level packaging, etc.</LI></UL> <P></P> <P>System–on–a–Chip <UL> <LI>Interconnect, design and processing of SOC, embedded memory processing, materials and integration, RF and high frequency passive components, MEMs and CMOS combinations,noise and cross–talk issues. <LI>Trade–offs between embedded memory and 3D</LI></UL> <P></P> <P>Novel Materials and Concepts <UL> <LI>Advanced interconnect concepts, optical interconnect, superconductors, nanotechnology–based interconnects, etc.</LI></UL>
Abbrevation
IITC
City
Burlingame
Country
United States
Deadline Paper
Start Date
End Date
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