<TABLE cellSpacing=0 cellPadding=0 width=″95%″ align=right border=0> <TBODY> <TR class=font–green–11> <TD width=″50%″> <UL> <LI>RF, analog and mixed–signal circuits <LI>Sensors and interface circuits <LI>Digital circuits and ASIC <LI>CPU, DSP and multicore architectures <LI>Memory circuits and systems <LI>Low power logic and architectures <LI>Multimedia processing circuits <LI>Communication circuits <LI>Embedded systems and software <LI>Designs using novel technologies <LI>System–in–package design <LI>Electronic System Level Design </LI></UL></TD> <TD> <UL> <LI>Modeling and simulation <LI>Hardware–software co–design <LI>Logic and architecture synthesis <LI>Physical design and verification <LI>Design for manufacturability <LI>Power estimation and optimization <LI>Design verification <LI>Test generation and fault simulation <LI>BIST and design for testability <LI>RF, analog and mixed–signal test <LI>SOC and system level testing <LI>System level design automation </LI></UL></TD></TR></TBODY></TABLE>
Abbrevation
VLSI-DAT
City
Taiwan
Country
China
Deadline Paper
Start Date
End Date
Abstract