<P><SPAN lang=EN–GB style=″FONT–SIZE: 9pt; FONT–FAMILY: Tahoma″><SPAN lang=EN–US style=″COLOR: black″></SPAN></SPAN><SPAN lang=EN–GB style=″FONT–SIZE: 9pt; FONT–FAMILY: Tahoma″></SPAN>Single chip embedded systems are becoming increasingly complex and heterogeneous. Such Systems–on–Chip (SoCs) require seamless integration of numerous IP cores performing different functions and operating at different clock frequencies. Network–on–Chip (NoC) is generally viewed as the ultimate solution for the design of modular and scalable communication architectures, and provides inherent support to the integration of heterogeneous cores through the standardization of the network interfaces. This workshop is focused on issues related to design, analysis and testing of on–chip networks.</P> <P><STRONG>Keywords:</STRONG> </P> <LI>Architectures and Topologies for NoCs and MPSoCs <LI>Routing algorithms and Router Micro–architectures <LI>Fault tolerance, reliability and testing issues <LI>Dynamic on–chip network reconfiguration <LI>Modeling and evaluation of on–chip networks <LI>Design space exploration and tradeoff analysis <LI>On–chip interconnection network simulators and emulators <LI>Industrial case studies of SoC designs using the NoC paradigm </LI>
Abbrevation
NoCArc
City
Lake Como
Country
Italy
Deadline Paper
Start Date
End Date
Abstract