<pre>The TAU series of workshops provide an informal forum for<br>> practitioners and researchers working on temporal aspects of<br>> digital systems to disseminate early work and engage in a<br>> free discussion of ideas. The sixteenth in the TAU series,<br>> the TAU 2009 workshop invites submissions from all areas<br>> related to the timing properties of digital electronic<br>> systems, including but not limited to:<br>><br>> Topics:<br>> Formal theories and methods<br>> System–level timing<br>> Transistor–level timing<br>><br>> Circuit–level timing<br>> Sensitivity analysis<br>> Full custom design analysis<br>> Integrated functional–temporal analysis<br>> Incremental analysis<br>> Timing issues in low power design<br>> Power–delay trade–offs<br>> Adjacent line switching and coupling<br>> Delay models and metrics<br>><br>> Layout impact on timing<br>> Timing–driven layout optimization<br>> Timing–driven synthesis and re–synthesis<br>> Circuit optimization<br>> Uncertainty–based analysis<br>> Incorporation of RETs in timing<br>> Reliability impact on performance<br>> Process & environmental variation models<br>> Statistical analysis techniques<br>> Clocking, synchronization, and skew<br>> Clock domains, static/dynamic logic<br>> Novel clocking schemes<br>> Special circuit families </pre>
Abbrevation
TAU
City
Austin
Country
United States
Deadline Paper
Start Date
End Date
Abstract