<P>Dedicated to advances, research, development and applications in the area of wafer manufacturing, circuit design, assembling and system engineering, and <STRONG>radio frequency integrated circuits, technologies and applications</STRONG> as the focus of this year, the overall content of <STRONG>SCD 2009</STRONG> includes, but is not limited to:</P> <P><STRONG>Chip, Packaging, Design, Simulation and Test </STRONG><BR><B>Keywords:</B> </P> <P> <TABLE class=fliesstext cellSpacing=0 cellPadding=0 width=515 border=0> <TBODY> <TR> <TD vAlign=top colSpan=3><SPAN class=Stil1><STRONG><FONT face=Verdana color=#003366 size=1>Major Topics</FONT></STRONG></SPAN></TD></TR> <TR> <TD vAlign=top colSpan=3> </TD></TR> <TR> <TD vAlign=top colSpan=3><SPAN class=Stil8></SPAN></TD></TR> <TR> <TD vAlign=top align=left width=4 rowSpan=15> <P class=Stil9> </P> <P class=Stil9> </P> <P class=Stil9> </P> <P class=Stil9> </P> <P class=Stil9> </P> <P class=Stil9> </P> <P class=Stil9> </P></TD> <TD vAlign=top width=19><STRONG><STRONG><STRONG><STRONG><IMG height=13 alt=″″ src=″http://www.gerotron.com/image/home/vier_punkte.gif″ width=10 align=textTop></STRONG></STRONG></STRONG></STRONG></TD> <TD vAlign=top width=492><SPAN class=Stil9><FONT size=1><FONT color=#003366><FONT face=Verdana><STRONG>Semiconductor Technologies, Materials and Processes:</STRONG> <BR>Silicon on insulator, strained silicon, aggressively scaled CMOS, SiGe, GaN, GaP, advances and application of adhesives, encapsulants, underfills, solder alloys, halogen–free materials, dielectrics, thin films, ceramics, composites, nano–materials, optical materials and characterization techniques, wafer (prime) production, CMP, HFP</FONT></FONT></FONT></SPAN></TD></TR> <TR> <TD vAlign=top> </TD> <TD vAlign=top> </TD></TR> <TR> <TD vAlign=top><STRONG><STRONG><STRONG><STRONG><IMG height=13 alt=″″ src=″http://www.gerotron.com/image/home/vier_punkte.gif″ width=10 align=textTop></STRONG></STRONG></STRONG></STRONG></TD> <TD vAlign=top><SPAN class=Stil9><FONT size=1><FONT color=#003366><FONT face=Verdana><STRONG>Assembly and Manufacturing Technologies:</STRONG> <BR>Wafer bumping and thinning, process characterization, cost and cycle time reduction</FONT></FONT></FONT></SPAN></TD></TR> <TR> <TD vAlign=top> </TD> <TD vAlign=top> </TD></TR> <TR> <TD vAlign=top><STRONG><STRONG><STRONG><STRONG><IMG height=13 alt=″″ src=″http://www.gerotron.com/image/home/vier_punkte.gif″ width=10 align=textTop></STRONG></STRONG></STRONG></STRONG></TD> <TD vAlign=top><SPAN class=Stil9><FONT size=1><FONT color=#003366><FONT face=Verdana><STRONG>Quality and Reliability:</STRONG> <BR>Component, board and system level reliability assessment, failure analysis, interfacial adhesion, accelerated testing and models, component and system qualification</FONT></FONT></FONT></SPAN></TD></TR> <TR> <TD vAlign=top> </TD> <TD vAlign=top> </TD></TR> <TR> <TD vAlign=top><STRONG><STRONG><STRONG><STRONG><IMG height=13 alt=″″ src=″http://www.gerotron.com/image/home/vier_punkte.gif″ width=10 align=textTop></STRONG></STRONG></STRONG></STRONG></TD> <TD vAlign=top><SPAN class=Stil9><FONT size=1><FONT color=#003366><FONT face=Verdana><STRONG>Interconnection Technologies:</STRONG> <BR>Wire bonding, flip chip (eutectic/lead–free solders), solder replacement flip chip (ICP, ACP, ACF, NCP), under bump metallurgy, high density substrates, microvia, build–up technologies, substrate metallurgy, embedded passives & actives, wafer/device level, MEMS, 3D and novel interconnects</FONT></FONT></FONT></SPAN></TD></TR> <TR> <TD vAlign=top> </TD> <TD vAlign=top> </TD></TR> <TR> <TD vAlign=top><STRONG><STRONG><STRONG><STRONG><IMG height=13 alt=″″ src=″http://www.gerotron.com/image/home/vier_punkte.gif″ width=10 align=textTop></STRONG></STRONG></STRONG></STRONG></TD> <TD vAlign=top><SPAN class=Stil9><FONT size=1><FONT color=#003366><FONT face=Verdana><STRONG>Modeling & Simulation: </STRONG><BR>EDA, electrical, thermal, thermo–mechanical, reliability, optical modeling and simulation for component and system level applications</FONT></FONT></FONT></SPAN></TD></TR> <TR> <TD vAlign=top> </TD> <TD vAlign=top> </TD></TR> <TR> <TD vAlign=top><STRONG><STRONG><STRONG><STRONG><IMG height=13 alt=″″ src=″http://www.gerotron.com/image/home/vier_punkte.gif″ width=10 align=textTop></STRONG></STRONG></STRONG></STRONG></TD> <TD vAlign=top><SPAN class=Stil9><FONT size=1><FONT color=#003366><FONT face=Verdana><STRONG>Integrated Circuit Design:</STRONG> <BR>RF, mixed–signal, analogue and digital systems and circuits for high speed, low power consumption, low costs, and advanced performance and density, application of aggressively scaled CMOS of 90 nm and below</FONT></FONT></FONT></SPAN></TD></TR> <TR> <TD vAlign=top> </TD> <TD vAlign=top> </TD></TR> <TR> <TD vAlign=top><STRONG><STRONG><STRONG><STRONG><IMG height=13 alt=″″ src=″http://www.gerotron.com/image/home/vier_punkte.gif″ width=10 align=textTop></STRONG></STRONG></STRONG></STRONG></TD> <TD vAlign=top><SPAN class=Stil9><FONT size=1><FONT color=#003366><FONT face=Verdana><STRONG>Advanced System and Wafer Level Packaging: </STRONG><BR>New packaging technologies for single chip, multi–chip, wafer level, power and stacked–die packages addressing fine pitch, high I/O and performance issues</FONT></FONT></FONT></SPAN></TD></TR> <TR> <TD vAlign=top> </TD> <TD vAlign=top> </TD></TR> <TR> <TD vAlign=top><STRONG><STRONG><STRONG><STRONG><IMG height=13 alt=″″ src=″http://www.gerotron.com/image/home/vier_punkte.gif″ width=10 align=textTop></STRONG></STRONG></STRONG></STRONG></TD> <TD vAlign=top><SPAN class=Stil9><FONT size=1><FONT color=#003366><FONT face=Verdana><STRONG>Optical and MEMS Packaging:</STRONG> <BR>Optical component assemblies, electro–optical modules, waveguides, Inertial MEMS, RF, Optical & Bio MEMS</FONT></FONT></FONT></SPAN></TD></TR></TBODY></TABLE></P>
Abbrevation
SCD
City
Dresden
Country
Germany
Deadline Paper
Start Date
End Date
Abstract