<br>The growing complexity and shrinking geometries of modern device technologies are making these high–density, low–voltage devices increasingly susceptible to influences from electrical noise, process variation, and natural radiation interference. System–level effects of these errors can be far reaching. Growing concern about intermittent errors, erratic storage cells, and the effects of aging are influencing system design. This workshop provides a forum for discussing current research and practices in system–level error management. Participants from industry and academia explore both current technologies and future research direction (including nanotechnology). We are interested in soliciting papers that cover system–level effects of errors from a variety of perspectives: architectural, logical and circuit–level, and semiconductor processes. Case studies are also solicited. <p>Key areas of interest are (but not limited to): </p> <ul><li>Technology trends and the impact on error rates. </li><li>New error mitigation techniques. </li><li>Characterizing the overhead and design complexity of error mitigation techniques. </li><li>Case studies describing the engineering tradeoffs necessary to decide what mitigation technique to apply. </li><li>Experimental data. </li><li>System–level models: derating factors and validation of error models. </li><li>Error handling protocols (higher–level protocols for robust system design).</li></ul>
Abbrevation
SELSE
City
Stanford
Country
United States
Deadline Paper
Start Date
End Date
Abstract