<pre>The quest for high–performance has lead to a reckless<br>> competition between chip manufacturers. Only two remain which<br>> can withstand the cost pressure of fabricating 45 nm designs.<br>> Today, the integration of four cores is common<br>> – and the end of the road is not in sight.<br>> The more transistors are integrated on a chip,<br>> the more faults can be asserted.<br>> These faults can arise either during operation or in<br>> fabrication. As the fabrication costs are continuously<br>> rising, it is most important to increase the output of a fab<br>> by architectural or physical means. The workshop addresses<br>> solutions to reach the goal of maximizing the (usable) output<br>> of a fab through dependable software or hardware designs of<br>> multi–core systems.<br>><br>><br>> The Workshop supports (but is not limited to) the following topics:<br>><br>> . Dependable Multi–Core Architectures<br>><br>> · Fault Detection on the Physical Layer<br>><br>> · Fault–Tolerant Software Design<br>><br>> · Power–Aware Design<br>><br>> · Fault–Tolerant Hardware Design<br>><br>> · Fault–Tolerant HW/SW Co–Design<br>><br>> · On–Chip Routing/ Scheduling<br>><br>> · Reconfigurable Computing and FPGA<br>><br>> · Dependability through Multi–Threading<br>><br>> · Fab–Aware Scheduling<br>><br>> · Simulation Techniques<br>><br>> · Trusted and Untrusted Environments</pre>
Abbrevation
IWCMC
City
Leipzig
Country
Germany
Deadline Paper
Start Date
End Date
Abstract