<p>IP – ESC 2009 (IP–Embedded Systems Conference) will be the 18th edition of the working conference on hot topics in the design world, focusing for the past 8 years on IP–based SoC design, held in the renowned Silicon Valley of the French Alps.<br>This event has grown regularly and the last edition in December, IP08, despite a depressed market, attracted over 400 attendees, mainly engineering managers. The satisfaction level of the attendees is impressive due to well focused, high level panels, sessions and seminars. Over the year IPs have become Subsystems or Platforms and thus as a natural extension IP 09 will be combined with Embedded Systems Conference to become IPESC 2009 addressing a continuous technical spectrum from IP to SoC to Embedded System. This will definitively leverage the participation in this new combined forum for attendees facing travel restrictions. This offers a fantastic opportunity to bring two well established brands together and deliver an even better event for delegates and vendors.<br>The global series of TechInsights Embedded Systems Conferences (ESC) are must attend events for embedded systems engineers, bringing together system architects, design engineers, suppliers, analysts and media across the globe. Every ESC event is a place for the embedded community to congregate, to identify solutions for immediate design challenges and to meet providers face–to–face, delivering solutions for their current project and the next. ESC holds itself true to the motto ′Learn today. Design tomorrow.′ in every facet of the event organization.<br>The areas of interest for the IP & ESC 09 event include (but are not restricted to): </p><p><b>IP Best practice </b><br>• Business models<br>• IP Exchange, reuse practice and design for reuse<br>• IP standards & reuse<br>• Collaborative IP based design<br><b>Design </b><br>• IP packaging for Integration<br>• IP and system configurability<br>• IP platform based design<br>• IP integration in NoC<br>• DFM and process variability in IP design<br><b>Quality and verification </b><br>• IP / SoC quality assurance<br>• IP / SoC prototyping<br>• IP / SoC verification and virtual prototyping<br>• IP / SOC transaction level modelling<br><b>Architecture and System Validation </b><br>• SoC embedded systems<br>• Multi–processor platforms<br>• HW/SW integration<br>• System–level analysis<br>• System–level virtual prototyping<br><b>Embedded Software </b><br>• Language requirements<br>• Compilation and code generation<br>• Model–based and graphical development<br>• Software analysis and debugging<br>• Software quality and verification<br><b>Real–Time and Fault Tolerant Systems </b><br>• Operating system requirements<br>• Real–time determinism<br>• Memory allocation<br>• Real–time network architectures </p>New topics are welcome –– please contact us at <a href=″mailto:ipesc09@design–reuse.com″>ipesc09@design–…;
Abbrevation
IP - ESC
City
Grenoble
Country
France
Deadline Paper
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End Date
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