International Workshop on Power and Timing Modeling, Optimization and Simulation, 2009, Delft, Niederlande

Abbrevation

PATMOS

Link

http://www.patmos-conf.org

City

Delft

Country

Netherlands

Deadline Paper

2009-05-20

Start Date

2009-09-09

End Date

2009-09-11

Abstract

PATMOS 2009 is the nineteenth in a series of international workshops. The PATMOS meeting has evolved into a leading scientific event where industry and academia meet to discuss power and timing aspects in modern integrated circuit and system design. PATMOS 2009 is organized by Delft University of Technology. The PATMOS objective is to provide a forum to discuss and investigate emerging challenges in methodologies and tools for the design of upcoming generations of integrated circuits and systems, including reconfigurable hardware such as FPGA′s. The technical program will focus on timing, performance and power consumption as well as architectural aspects with particular emphasis on modeling, design, characterization, analysis and optimization. The emphasis of the workshop is on, but not limited to, the following topics: * Timing and Performance – Methodologies and tools for the analysis, design and verification of timing and performance properties of integrated circuits and systems at all levels of abstraction; – Variability and statistical timing analysis; – Design for yield, design for manufacturability; – Special timing or performance related topics, e.g. crosstalk, synchronization, GALS, side–channel attacks. * Power Dissipation – Design techniques for low power circuits and systems at all levels of abstraction; – Methods and tools for analysis, characterization, design and optimization of the power consumption; – Low power architectures and libraries; – Special power related topics, e.g. low voltage, leakage power, power grid, interconnect power, clock tree power, power aware test pattern generation, thermal effects. * Design Experience and Case Studies – Examples, test cases, benchmarks or design studies which present innovative solutions for timing, performance or power consumption related design challenges. * Power and Timing Issues Addressing Specific Technologies – Reconfigurable Architectures; – Caches and Memory Devices; – Low Power Software.