<SPAN style="FONT–FAMILY: Arial; FONT–SIZE: 10pt" lang=EN–GB>Increased manufacturing susceptibility in today’s <SPAN class=SpellE>nanometer</SPAN> technologies requires up to date solutions for yield optimization. In fact, designing <SPAN class=GramE>an</SPAN> <SPAN class=SpellE>SoC</SPAN> for manufacturability and yield aim at improving the manufacturing process and consequently its yield by enhancing communications across the design – manufacturing interface. A wide range of Design–for–Manufacturability (DFM) and Design–for–Yield (DFY) methodologies and tools are proposed today. Some of which are leveraged during the back–end design stages, and others have post design utilization, from lithography up to wafer sort, packaging, final test and failure analysis. DFM can dramatically impact the business performance of chip manufacturers. It can also significantly affect age–old chip design flows. Using a DFM solution is an investment and thus choosing the most cost effective one(s) requires trade–off analysis. The workshop analyzes this key trend and its challenges, and gives the opportunity to discuss a range of DFM and DFY solutions for today′s SoC designs.</SPAN>
Abbrevation
dfm&y
City
San Francisco, CA
Country
United States
Deadline Paper
Start Date
End Date
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