<span class="Apple–style–span" style="border–collapse: separate; color: rgb(0, 0, 0); font–family: ′Times New Roman′; font–style: normal; font–variant: normal; font–weight: normal; letter–spacing: normal; line–height: normal; orphans: 2; text–indent: 0px; text–transform: none; white–space: normal; widows: 2; word–spacing: 0px; font–size: medium;"><span class="Apple–style–span" style="font–family: Arial,Helvetica,FreeSans,′Liberation Sans′,′Nimbus Sans L′,sans–serif; font–size: 12px;">3–D ICs enable dramatically improved performances at a much lower cost than new leading–edge CMOS technology below 32 nm transistor fabrication. The success of these new ICs depends on the availability of new methodologies and skills that are required to achieve acceptable design quality and productivity. This workshop brings together key actors from semiconductor companies, system design houses and EDA industry to build a vision of the next step in 3D integrated ICs design. Topics addressed are: Applications requiring 3D, interconnect architectures and thermal management for 3D ICs, application partitioning, floor planning for 3D architectures, modeling, characterization and testing for 3D ICs.</span></span>
Abbrevation
IEEE D43D-CMOSAIC
Link
City
Lausanne
Country
Switzerland
Start Date
End Date
Abstract