First IEEE International Workshop on Testing Three-Dimensional Stacked Integrated Circuits, Austin, Vereinigte Staaten

The new 3D–TEST Workshop focuses exclusively on test of and design–for–test for three–dimensional stacked ICs (3D–SICs), including Systems–in–Package (SiP), Package–on–Package (PoP), and especially 3D–SICs based on Through–Silicon Vias (TSVs). While 3D–SICs offer many attractive advantages with respect to heterogeneous integration, smaller form–factor, higher bandwidth and performance, and lower power dissipation, there are many open issues with respect to testing such products. The 3D–TEST Workshop offers a forum to present and discuss these challenges and (emerging) solutions among researchers and practitioners alike.