Abbrevation
DDECS
City
Cottbus
Country
Germany
Deadline Paper
Start Date
End Date
Abstract

<PRE><PRE>The IEEE Symposium on Design and Diagnostics of Electronic Circuits and<BR>Systems provides a forum for exchanging ideas, discussing research results, and<BR>presenting practical applications in the areas of design, test, and diagnosis of<BR>nanoelectronic circuits and systems&#046; The symposium also offers an insight into<BR>relevant European R&amp;D collaborative programs, projects, and technology platforms&#046;<BR>The DDECS Symposium series has been organised by Central European countries:<BR>Czech Republic (1997, 2002, 2006, 2009), Poland (1998, 2003, 2007), Slovakia (2000,<BR>2004, 2008), Hungary (2001, 2005), and Austria (2010)&#046;</PRE><PRE>DDECS 2011 is organised by Brandenburg University of Technology Cottbus and<BR>the Leibniz Institute IHP &#8211; "Innovations for High&#8211;Performance Microelectronics"<BR>in Frankfurt (Oder), Germany&#046; The symposium is sponsored by the IEEE Computer<BR>Society Test Technology Technical Council (TTTC)&#046;</PRE><PRE>Topics of interest include but are not limited to:<BR>&#8211; ASIC and SoC Design<BR>&#8211; FPGA Design<BR>&#8211; Bio&#8211;inspired Hardware<BR>&#8211; Design Verification/Validation<BR>&#8211; Formal Methods in System Design<BR>&#8211; Hardware/Software Co&#8211;Design<BR>&#8211; IP&#8211;based Design<BR>&#8211; Logic Synthesis<BR>&#8211; Physical Design<BR>&#8211; Design and Test in Nano&#8211;Technologies<BR>&#8211; Reconfigurable Computing<BR>&#8211; Network&#8211;based Collaborative Design<BR>&#8211; Analog, Mixed&#8211;Signal, and RF Test<BR>&#8211; SoC Test<BR>&#8211; Built&#8211;in Self&#8211;Test and Self&#8211;Repair<BR>&#8211; Design for Testability and Diagnosis<BR>&#8211; Defect/Fault Tolerance and Reliability<BR>&#8211; On&#8211;line Testing<BR>&#8211; Embedded Systems Testing<BR>&#8211; Memory, Processor Testing<BR>&#8211; MEMS Testing<BR>&#8211; ATE Hardware and Software<BR>&#8211; Dependable HW / SW Systems</PRE></PRE>