<PRE><P class=bodytext>The <B>IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems</B> <BR>provides a forum for exchanging ideas, discussing research results and presenting practical applications in<BR>the areas of design, test and diagnosis of microelectronic circuits and systems. </P><P class=bodytext><BR>The <B>DDECS Workshop/Symposium series</B> is organised by Central European countries: Czech Republic<BR>(1997, 2002, 2006, 2009), Poland (1998, 2003, 2007), Slovakia (2000, 2004, 2008) and Hungary (2001,<BR>2005). <B>DDECS 2010</B> will, for the first time, take place in Vienna, the romantic yet vivid capital of Austria.<BR>The Symposium is organised by the Vienna University of Technology and sponsored by the Test<BR>Technology Technical Council (TTTC) of the IEEE Computer Society. </P><P class=bodytext> </P><P class=bodytext><TABLE class=contenttable style="WIDTH: 100%" cellSpacing=2 cellPadding=5 width="100%"><TBODY><TR><TD class=align–left style="VERTICAL–ALIGN: top; WIDTH: 50%" width="50%"><UL><LI>ASIC/FPGA Design <LI>Bio–inspired Hardware <LI>Design Verification/Validation <LI>Formal Methods in System Design <LI>Hardware/Software Co–Design <LI>IP–based Design <LI>Logic Synthesis <LI>Physical Design <LI>ATE Hardware and Software <LI>SoC Design and Test</LI></UL></TD><TD class=align–left style="VERTICAL–ALIGN: top; WIDTH: 50%" width="50%"><UL><LI>Analog, Mixed–Signal, RF Design and Test <LI>Built–in Self–Test and Self–Repair <LI>Design for Testability and Diagnosis <LI>Defect/Fault Tolerance and Reliability <LI>On–line Testing <LI>Embedded Systems Testing <LI>Memory, Processor Testing <LI>MEMS Testing <LI>Design and Test in Nano–Technologies <LI>Educational Tools for Design and Test </LI></UL></TD></TR></TBODY></TABLE></P></PRE>
Abbrevation
DDECS
City
Wien
Country
Austria
Deadline Paper
Start Date
End Date
Abstract