Abbrevation
NOCS
City
PittsburghPA
Country
United States
Deadline Paper
Start Date
End Date
Abstract

NOCS is the premier event dedicated to interdisciplinary research on on&#8211;chip communication technology, architecture, design methods and applications, bringing together scientists and engineers working on NoC innovations from inter&#8211;related research communities, including computer architecture, networking, circuits and systems, embedded systems, and design automation&#046; <P>This year, NOCS 2010 will be collocated with the 16th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC 2010)&#046; The two symposia will be hosted by CEA&#8211;LETI in MINATEC&#046; The organization and the programs of both symposia will be jointly coordinated, including keynote lectures, tutorials, exhibitions and social events&#046;<BR>See <A href="http://www&#046;minatec&#046;org/async&#8211;nocs2010/&quot; target=_blank>http://www&#046;minatec&#046;org/async&#8211;nocs2010/</A></P&gt; <P class=MsoPlainText style="MARGIN: 0cm 0cm 0pt"><FONT face=Arial>* Network architecture (topology, routing, arbitration)</FONT></P> <P class=MsoPlainText style="MARGIN: 0cm 0cm 0pt"><FONT face=Arial>* Network design for 3D stacked logic and memory</FONT></P> <P class=MsoPlainText style="MARGIN: 0cm 0cm 0pt"><FONT face=Arial>* Mapping of applications onto NoCs</FONT></P> <P class=MsoPlainText style="MARGIN: 0cm 0cm 0pt"><FONT face=Arial>* Power and energy issues</FONT></P> <P class=MsoPlainText style="MARGIN: 0cm 0cm 0pt"><FONT face=Arial>* Timing, synchronous/asynchronous communication</FONT></P> <P class=MsoPlainText style="MARGIN: 0cm 0cm 0pt"><FONT face=Arial>* NoC reliability issues</FONT></P> <P class=MsoPlainText style="MARGIN: 0cm 0cm 0pt"><FONT face=Arial>* OS support for NoCs and programming models</FONT></P> <P class=MsoPlainText style="MARGIN: 0cm 0cm 0pt"><FONT face=Arial>* workload characterization &amp; evaluation <SPAN style="mso&#8211;tab&#8211;count: 1"> </SPAN></FONT></P> <P class=MsoPlainText style="MARGIN: 0cm 0cm 0pt"><FONT face=Arial>* Network interface issues</FONT></P> <P class=MsoPlainText style="MARGIN: 0cm 0cm 0pt"><FONT face=Arial>* Modeling, simulation, and synthesis of NoCs</FONT></P> <P class=MsoPlainText style="MARGIN: 0cm 0cm 0pt"><FONT face=Arial>* NoC support for memory and cache access</FONT></P> <P class=MsoPlainText style="MARGIN: 0cm 0cm 0pt"><FONT face=Arial>* NoC design methodologies and tools</FONT></P> <P class=MsoPlainText style="MARGIN: 0cm 0cm 0pt"><FONT face=Arial>* NoC Quality of Service</FONT></P> <P class=MsoPlainText style="MARGIN: 0cm 0cm 0pt"><FONT face=Arial>* NoCs for FPGAs and structured ASICs</FONT></P> <P class=MsoPlainText style="MARGIN: 0cm 0cm 0pt"><FONT face=Arial>* NoC support for CMP/MPSoCs</FONT></P> <P class=MsoPlainText style="MARGIN: 0cm 0cm 0pt"><FONT face=Arial>* Novel interconnect links/switches/routers</FONT></P> <P class=MsoPlainText style="MARGIN: 0cm 0cm 0pt"><FONT face=Arial>* Optical &amp; RF for on&#8211;chip/in&#8211;package interconnects</FONT></P> <P class=MsoPlainText style="MARGIN: 0cm 0cm 0pt"><FONT face=Arial>* Signaling and circuit design for NoC links</FONT></P> <P class=MsoPlainText style="MARGIN: 0cm 0cm 0pt"><FONT face=Arial>* Physical design of interconnect and NoC</FONT></P> <P class=MsoPlainText style="MARGIN: 0cm 0cm 0pt"><FONT face=Arial>* Verification, debug &amp; test of NoCs</FONT></P> <P class=MsoPlainText style="MARGIN: 0cm 0cm 0pt"><FONT face=Arial>* Metrics and benchmarks for NoCs</FONT></P> <P class=MsoPlainText style="MARGIN: 0cm 0cm 0pt"><FONT face=Arial>* NoC case studies, application&#8211;specific NoC design</FONT></P>