The 17th IEEE International Symposium on Asynchronous Circuits and Systems, Ithaca, Vereinigte Staaten

Abbrevation

ASYNC

Link

http://asyncsymposium.org/async2011/Home.html

City

Ithaca

Country

United States

Deadline Paper

2010-11-08

Start Date

2011-04-27

End Date

2011-04-29

Abstract

<SPAN class=Apple–style–span style="WORD–SPACING: 0px; FONT: medium ′Times New Roman′; TEXT–TRANSFORM: none; COLOR: rgb(0,0,0); TEXT–INDENT: 0px; WHITE–SPACE: normal; LETTER–SPACING: normal; BORDER–COLLAPSE: separate; orphans: 2; widows: 2"> The International Symposium on Asynchronous Circuits and Systems is the premier forum for researchers to present their latest findings in the area of asynchronous design. Authors are invited to submit full papers on any aspect of asynchronous design, ranging from the core topics of design, synthesis, and test, to asynchronous applications in system–level integration and emerging computing technologies. Topics of interest include, but are not limited to: <OL> <LI class=full–width style="PADDING–LEFT: 24px; TEXT–INDENT: –8px; LINE–HEIGHT: 14px"> â€¢Asynchronous/mixed–timed circuits, architectures, memories and interfaces, including interfaces with analogue and mixed–signal domains <LI class=full–width style="PADDING–LEFT: 24px; TEXT–INDENT: –8px; LINE–HEIGHT: 14px"> â€¢Design models and methods for asynchronous buses, networks on chip (NoC), system–on–chip (SoC), and multi–chip interconnects <LI class=full–width style="PADDING–LEFT: 24px; TEXT–INDENT: –8px; LINE–HEIGHT: 14px"> â€¢Asynchronous power–adaptive computing, ultra–low power systems, and electronics for energy harvesting <LI class=full–width style="PADDING–LEFT: 24px; TEXT–INDENT: –8px; LINE–HEIGHT: 14px"> â€¢Asynchrony in emerging technologies, including genetic, neural, nano, and quantum computing <LI class=full–width style="PADDING–LEFT: 24px; TEXT–INDENT: –8px; LINE–HEIGHT: 14px"> â€¢Embedded system design with asynchronous architectures/implementations <LI class=full–width style="PADDING–LEFT: 24px; TEXT–INDENT: –8px; LINE–HEIGHT: 14px"> â€¢Elastic and latency–tolerant synchronous design and GALS systems <LI class=full–width style="PADDING–LEFT: 24px; TEXT–INDENT: –8px; LINE–HEIGHT: 14px"> â€¢CAD tools for asynchronous design, synthesis, analysis, and optimization <LI class=full–width style="PADDING–LEFT: 24px; TEXT–INDENT: –8px; LINE–HEIGHT: 14px"> â€¢Synchronization, arbitration, metastability modeling, and analysis <LI class=full–width style="PADDING–LEFT: 24px; TEXT–INDENT: –8px; LINE–HEIGHT: 14px"> â€¢Physical design of asynchronous logic and pipelines <LI class=full–width style="PADDING–LEFT: 24px; TEXT–INDENT: –8px; LINE–HEIGHT: 14px"> â€¢Formal methods for correctness validation and for performance/power analysis <LI class=full–width style="PADDING–LEFT: 24px; TEXT–INDENT: –8px; LINE–HEIGHT: 14px"> â€¢Test, reliability, security, and radiation tolerance <LI class=full–width style="PADDING–LEFT: 24px; TEXT–INDENT: –8px; LINE–HEIGHT: 14px"> â€¢Asynchronous variability–tolerant design and design for manufacturing <LI class=full–width style="PADDING–LEFT: 24px; TEXT–INDENT: –8px; LINE–HEIGHT: 14px"> â€¢Motivating case studies, comparisons, and applications </LI></OL>