Workshop on Micro Power Management for Macro Systems on Chip, Grenoble, Frankreich

Abbrevation

uPM2SoC

Link

http://www.ece.cmu.edu/~dianam/uPM2SoC10/

City

Grenoble

Country

France

Deadline Paper

2010-11-19

Start Date

2011-03-18

End Date

2011-03-18

Abstract

Increased integration of hundreds of processing cores on the same silicon substrate has allowed the concurrent execution of multiple applications on a chip, but at the cost of significant increase in on–chip power consumption. On–chip power management has therefore become a critical component of every step in the many–core design flow, from physical design all the way up to micro–architecture and system–level design. While dynamic power management has been extensively studied for the case of single–core systems, many–core systems present additional challenges that require maintaining appropriate performance levels for applications running on the system both in the context of turning on/off cores and using selectively power states, or in the context of using Dynamic Voltage Frequency Scaling (DVFS) for enabling a certain performance level at a minimum power. Furthermore, enabling power management at macroscale –for hundreds or thousands of on–chip resources– while relying on capabilities developed at microscale –specifically, technology and device–level knobs– becomes essential for effective power control. <?xml:namespace prefix = o ns = "urn:schemas–microsoft–com:office:office" /> This workshop addresses this need by targeting emerging topics in power management and control of large scale many–core systems, such as scalability, distributed vs. centralized vs. hybrid approaches, as well as technology–driven challenges that need to be considered for providing a truly power–aware solution, such as static and dynamic variations and reliability, as well as limits for control strategies for technologies 22nm and beyond.