The International Conference on Computer Design, Amherst, Vereinigte Staaten

Abbrevation

ICCD

Link

http://iccd-conference.com

City

Amherst

Country

United States

Deadline Paper

2011-05-13

Start Date

2011-10-09

End Date

2011-10-12

Abstract

<SPAN style="FONT–FAMILY: ′–moz–fixed′,′serif′; FONT–SIZE: 10pt; mso–fareast–font–family: Calibri; mso–fareast–theme–font: minor–latin; mso–bidi–font–family: ′Times New Roman′; mso–ansi–language: DE; mso–fareast–language: DE; mso–bidi–language: AR–SA">The International Conference on Computer Design encompasses a wide range of topics in the research, design, and implementation of computer systems and their components. ICCD′s multi–disciplinary emphasis provides an ideal environment for developers and researchers to discuss practical and theoretical work covering system and computer architecture, verification and test, design and technology, and tools and methodologies. The theme for the 2011 ICCD conference is: – Pervasive Computing – Submitted papers consistent with this theme are encouraged, but manuscripts describing original work on any topic within the scope of ICCD are welcome. Authors are asked to submit technical papers in accordance to the author′s instructions in one of the following five conference tracks: Computer Systems and Applications: * Advanced computer architecture for general and application–specific enhancement; * Software design for embedded, mobile, general–purpose, cloud, and high–performance platforms; * IP and platform–based designs; * HW/SW co–design; * Modeling and performance analysis; * Support for security, languages and operating systems; * Real–time systems; Application–specific and embedded software optimization; * Optimizing and parallelizing compiler support for multithreaded and multi–core designs; * Memory system and network system optimization; * On–chip and system–area networks; * Support for communication and synchronization (e.g., transactional memory). Processor Architecture: * Microarchitecture design techniques for uni– and multi–core processors: instruction–level parallelism, pipelining, caching, branch prediction, multithreading; * Techniques for low–power, secure, and reliable processor designs; * Embedded, network, graphic, system–on–chip, application–specific and digital signal processor design; * Hardware support for processor virtualization; * Real–life design challenges: case studies, tradeoffs and post–mortems. Logic and Circuit Design: * Circuits and design techniques for digital, memory, analog and mixed–signal systems; * Circuits and design techniques for high performance and low power; * Circuits and design techniques for robustness under process variability and radiation; * Design techniques for emerging process technologies (MEMs, spintronics, nano, quantum); * Asynchronous circuits; * Signal processing and arithmetic circuits, and circuits for graphic processor design. Electronic Design Automation: * High–level, logic and physical synthesis; * Physical planning, design and early estimation for large circuits; * Automatic analysis and optimization of timing, power and noise; * Tools for multiple–clock domains, asynchronous and mixed timing methodologies; * CAD support for FPGAs, ASSPs, structured ASICs, platform–based design and networks–on– chip; * DfM and OPC methodologies; * System–level design; * System–level synthesis; * Tools, methodologies and design strategies for emerging technologies (MEMs, spintronics, nano, quantum). Verification and Test: * Functional, transaction–level, RTL, and gate–level modeling and verification of hardware designs; * Modeling, verification, and specification languages; * Simulation–based and formal techniques for design verification; * Assertion–based verification; * Equivalence checking, property checking, and theorem proving; * Coverage–analysis; * Constrained–random test generation; * High–level design validation; * Hardware/Software integration and hardware emulation; * SoC verification; * Design error debug and diagnosis; * Fault modeling; * Fault simulation and ATPG; * Fault tolerance; * DFT and BIST.