<P>The International Conference on Computer Aided Design (ICCAD) offers a place for CAD developers and IC designers to meet and exchange ideas about the problems and solutions in the era of system–on–a–chip. <B></B></P> <P><B>Schlüsselwörter:</B> </P> <P><STRONG>1) SYNTHESIS, VERIFICATION AND PHYSICAL DESIGN</STRONG></P> <P><STRONG>1.1 Logic and High–Level Synthesis:</STRONG></P> <P style="MARGIN–LEFT: 5pt">•Synthesis, technology mapping</P> <P style="MARGIN–LEFT: 5pt">•Refinement techniques</P> <P style="MARGIN–LEFT: 5pt">•Direct compilation and post–optimization</P> <P style="MARGIN–LEFT: 5pt">•Micro–architectural transformations</P> <P style="MARGIN–LEFT: 5pt">•Memory system synthesis</P> <P><STRONG>1.2 Simulation and Formal Verification:</STRONG></P> <P style="MARGIN–LEFT: 5pt">•Formal verification techniques</P> <P style="MARGIN–LEFT: 5pt">•HW/SW co–simulation</P> <P style="MARGIN–LEFT: 5pt">•Switch, logic, behavioral, and system–level simulation and validation</P> <P style="MARGIN–LEFT: 5pt">•Protocol and interface design for correctness</P> <P style="MARGIN–LEFT: 5pt">•Software verification</P> <P style="MARGIN–LEFT: 5pt">•Emulation</P> <P style="MARGIN–LEFT: 5pt">•Hybrid systems</P> <P style="MARGIN–LEFT: 5pt">•Post–silicon validation (for functional design errors)</P> <P><STRONG>1.3 Partitioning, Placement and Floorplanning:</STRONG></P> <P style="MARGIN–LEFT: 5pt">•High–level physical design and synthesis</P> <P style="MARGIN–LEFT: 5pt">•Estimation and hierarchy management</P> <P style="MARGIN–LEFT: 5pt">•Partitioning, floor–planning and global placement</P> <P style="MARGIN–LEFT: 5pt">•Detailed and incremental placement</P> <P><STRONG>1.4 Routing and Detailed Physical Design:</STRONG></P> <P style="MARGIN–LEFT: 5pt">•Detailed routing, including routing for yield, manufacturability, and timing</P> <P style="MARGIN–LEFT: 5pt">•Post–placement layout optimization.</P> <P><STRONG>1.5 Optimization in Physical Design:</STRONG></P> <P style="MARGIN–LEFT: 5pt">•Optimization for area, timing, power, and yield</P> <P style="MARGIN–LEFT: 5pt">•Interaction between physical design and logic synthesis. </P> <P><STRONG>2) SYSTEM–LEVEL CAD</STRONG></P> <P><STRONG>2.1 System Design:</STRONG></P> <P style="MARGIN–LEFT: 5pt">•System–level specification and modeling and simulation</P> <P style="MARGIN–LEFT: 5pt">•System design flows and methods</P> <P style="MARGIN–LEFT: 5pt">•Models of computation</P> <P style="MARGIN–LEFT: 5pt">•HW/SW co–design, co–optimization, and co–exploration</P> <P style="MARGIN–LEFT: 5pt">•HW/SW platforms</P> <P style="MARGIN–LEFT: 5pt">•Rapid prototyping</P> <P style="MARGIN–LEFT: 5pt">•System design case studies and applications</P> <P><STRONG>2.2 Embedded Systems Hardware:</STRONG></P> <P style="MARGIN–LEFT: 5pt">•Multi–core/multi–processors systems</P> <P style="MARGIN–LEFT: 5pt">•On–chip communication and networks–on–chip</P> <P style="MARGIN–LEFT: 5pt">•Static and dynamic reconfigurable architectures</P> <P style="MARGIN–LEFT: 5pt">•Regular circuits, structured ASICs</P> <P style="MARGIN–LEFT: 5pt">•Application–specific instruction–set processors (ASIPs)</P> <P style="MARGIN–LEFT: 5pt">•Memory hierarchies and management</P> <P style="MARGIN–LEFT: 5pt">•System–level issues for 3–D integration</P> <P><STRONG>2.3 Embedded Systems Software:</STRONG></P> <P style="MARGIN–LEFT: 5pt">•Real–time software and RTOS</P> <P style="MARGIN–LEFT: 5pt">•Middleware</P> <P style="MARGIN–LEFT: 5pt">•Timing analysis and WCET</P> <P style="MARGIN–LEFT: 5pt">•Programming models for multi–core systems</P> <P style="MARGIN–LEFT: 5pt">•Profiling and compilation techniques</P> <P><STRONG>2.4 Power and Thermal Considerations in System Design:</STRONG></P> <P style="MARGIN–LEFT: 5pt">•Power and thermal estimation, analysis, optimization, and management techniques for hardware and software systems</P> <P><STRONG>3) CAD FOR RELIABILITY, MANUFACTURABILITY, AND TEST</STRONG></P> <P><STRONG>3.1 Design for Manufacturability:</STRONG></P> <P style="MARGIN–LEFT: 5pt">•CAD for the design/manufacturing interface, CAD support for OPC and RET, variability analysis, yield estimation</P> <P style="MARGIN–LEFT: 5pt">•Manufacturable layout</P> <P><STRONG>3.2 Testing:</STRONG></P> <P style="MARGIN–LEFT: 5pt">•Fault modeling, delay test, analog and mixed signal test</P> <P style="MARGIN–LEFT: 5pt">•Fault simulation</P> <P style="MARGIN–LEFT: 5pt">•ATPG, BIST and DFT</P> <P style="MARGIN–LEFT: 5pt">•Memory test and repair</P> <P style="MARGIN–LEFT: 5pt">•Technology impact on test</P> <P style="MARGIN–LEFT: 5pt">•Post–silicon validation and debug (for electrical, physical, and timing issues)</P> <P><STRONG>3.3 Design for Reliability:</STRONG></P> <P style="MARGIN–LEFT: 5pt">•Design techniques for achieving reliability, resilience and robustness from unreliable components</P> <P style="MARGIN–LEFT: 5pt">•Analysis of thermal, reliability, aging, NBTI, electromigration, wearout, etc., effects in CMOS and mixed technologies and physical domains</P> <P style="MARGIN–LEFT: 5pt">•Reliability issues in system design and 3–D integration</P> <P><STRONG>4) CAD FOR CIRCUITS, DEVICES, AND INTERCONNECT </STRONG></P> <P><STRONG>4.1 Analog, Mixed–Signal, RF and Multi–Domain Simulation:</STRONG></P> <P style="MARGIN–LEFT: 5pt">•Numerical methods for analog, mixed–signal, RF, multi–domain (MEMS, nanoelectronic, optoelectronic, biological, etc.) network and system simulation</P> <P style="MARGIN–LEFT: 5pt">•Nonlinear model reduction and computational macromodeling</P> <P style="MARGIN–LEFT: 5pt">•Fast analysis of large–scale circuits and systems</P> <P style="MARGIN–LEFT: 5pt">•Computer–aided analysis, design, and simulation of electronic and mixed–domain devices including semiconductor, nanoelectronic, micromechanical, and electro–optical devices</P> <P style="MARGIN–LEFT: 5pt">•Compact device modeling and modeling of device variability</P> <P><STRONG>4.2 Analog, Mixed–Signal, RF and Multi–Domain Synthesis and Optimization:</STRONG></P> <P style="MARGIN–LEFT: 5pt">•Advances in low power, variation–aware, high speed design methodology and tools</P> <P style="MARGIN–LEFT: 5pt">•Structural synthesis, sizing, design centering, symbolic and formal analysis, constraint management</P> <P style="MARGIN–LEFT: 5pt">•Analog place and route</P> <P style="MARGIN–LEFT: 5pt">•Synthesis and design methods for MEMS, electro–optical, and other mixed technology systems</P> <P><STRONG>4.3 Timing and Behavioral Modeling:</STRONG></P> <P style="MARGIN–LEFT: 5pt">•Gate–, switch–, and block–level modeling</P> <P style="MARGIN–LEFT: 5pt">•Timing analysis and methodologies including statistical timing</P> <P style="MARGIN–LEFT: 5pt">•Current–source modeling</P> <P style="MARGIN–LEFT: 5pt">•Behavioral modeling of circuits and systems</P> <P><STRONG>4.4 Interconnect and Power Networks:</STRONG></P> <P style="MARGIN–LEFT: 5pt">•Network–level power/ground and package analysis and optimization</P> <P style="MARGIN–LEFT: 5pt">•Reduced order modeling of interconnect and linear time invariant networks</P> <P style="MARGIN–LEFT: 5pt">•Signal integrity analysis</P> <P style="MARGIN–LEFT: 5pt">•Interconnect parameter extraction</P> <P style="MARGIN–LEFT: 5pt">•Electromagnetic simulation and package analysis</P> <P style="MARGIN–LEFT: 5pt">•EMC/EMI simulation techniques</P> <P><STRONG>5) CAD FOR NANOSCALE AND BIOLOGICAL SYSTEMS</STRONG></P> <P><STRONG>5.1 Biological Systems:</STRONG></P> <P style="MARGIN–LEFT: 5pt">•Computer–aided analysis techniques for biologicalsystems–biomolecular, intracellular, cellular, organ and organism level</P> <P style="MARGIN–LEFT: 5pt">•Analysis and design of synthetic biological systems. Multi–scale biological systems, systems biology</P> <P><STRONG>5.2 Nanoscale and Post–CMOS Systems: </STRONG></P> <P style="MARGIN–LEFT: 5pt">•Analysis, synthesis and design methods for novel devices (eg., quantum, molecular, spin–based) and systems centered about future nanotechnologies</P> <P style="MARGIN–LEFT: 5pt">•Bio–electronic devices and systems.</P> <P>.</P> <P>.</P>
Abbrevation
ICCAD
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City
San Jose, CA
Country
United States
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