<ol style="FONT–FAMILY: arial; FONT–SIZE: 12px"> <li>Chip–Level Design for Signal/Power Integrity </li> <li>Analog and Mixed–Signal Design and Verification </li> <li>FPGA Design and Debug </li> <li>System Co–Design: Chip/Package/Board </li> <li>PCB Materials, Processing and Characterization </li> <li>PCB Design Tools and Methodologies </li> <li>Memory and Parallel Interface Design </li> <li>High–Speed Serial Design </li> <li>High–Speed Timing, Jitter and Noise Analysis </li> <li>High–Speed Signal Processing, Equalization and Coding </li> <li>Power Integrity and Power Distribution Network Design </li> <li>Electromagnetic Compatibility and Interference </li> <li>Test and Measurement Methodology </li> <li>RF/Microwave Techniques for Signal Integrity </li></ol>
Abbrevation
DesignCon
City
Santa Clara
Country
United States
Deadline Paper
Start Date
End Date
Abstract