<P><STRONG>Topic suggestions:</STRONG><BR>We encourage you to contribute your experiences with hardware design and verification languages, advanced tools and methodologies, and to participate in the valuable exchange of ideas.</P> <P>• Experience using ESL and/or TLM for system–level design and verification<BR>• Experiences deploying a verification methodology library<BR>• Experiences with System–on–Chip design<BR>• Designing and/or verifying complex ASICs and FPGAs<BR>• Using multiple HDLs and/or HVLs in a design cycle<BR>• Techniques for generating constrained–random test, or other automated stimulus generation methods<BR>• Synthesizing transaction–level or abstract designs from high–level languages such as SystemC, System Verilog or C++, to RTL<BR>• Experiences with hardware/software co–design and co–verification<BR>• Experiences with mixed–signal simulation<BR>• Verification techniques that really work (and what did not work)<BR>• Verification process and resource management<BR>• Assertion–based verification<BR>• Coverage–driven verification<BR>• Design and verification IP experiences, good and bad<BR>• Any topic involving the use of an HDL or HVL <BR>• Debug techniques for HVL testbenches and complex software–style testbenches<BR>• Debug techniques for SoCs with black–box and grey–box IP<BR>• Debug techniques for ESL and abstract models<BR>• Software engineering techniques for advanced testbenches focusing on efficiency for scalability<BR>• Experience with formal and semi–formal techniques<BR>• Experience with deployment of recently approved standards<BR></P>
Abbrevation
DVCon
City
San Jose
Country
United States
Deadline Paper
Start Date
End Date
Abstract