Intellectual Property for System-on-Chip 2011, Grenoble, Frankreich

Abbrevation

IP-SOC

Link

http://www.design-reuse.com/ipsoc2011/

City

Grenoble

Country

France

Deadline Paper

2011-09-24

Start Date

2011-12-07

End Date

2011-12-08

Abstract

About this Event... IP – SoC 2011 will be the 20th edition of the working conference on hot topics in the design world, focusing for the past 9 years on IP–based SoC design and held in the renowned Silicon Valley of the French Alps. This event is the only worldwide event fully dedicated to IP (Intellectual Property) in electronic systems. The satisfaction level of the attendees is impressive due to well focused, high level panels, sessions and seminars. Over the year IPs have become Subsystems or Platforms and thus as a natural applicative extension IP–SoC will definitively include a strong Embedded Systems track addressing a continuous technical spectrum from IP to SoC to Embedded System. Areas of interest: – IP Best practice – Business models – IP Exchange, reuse practice and design for reuse – IP standards & reuse – Collaborative IP based design Design – DFM and process variability in IP design – IP / SoC physical implementation – IP design and IP packaging for Integration – IP and system configurability – IP platform and Network on Chip Quality and verification – IP / SoC verification and prototyping – IP / SoC quality assurance–architecture and System – IP / SOC transaction level modelling – Multi–processor platforms – HW/SW integration – System–level analysis – System–level virtual prototyping – NoC–based Architecture Embedded Software – Software requirements (timeliness, reactivity) – Computational Models – Compilation and code generation Real–Time and Fault Tolerant Systems – Real–time or Embedded Computing Platforms – Real–Time resource management and Scheduling – Real–time Operating system – Support for QoS – Real–time system modelling and analysis – Energy–aware real–time systems