Abbrevation
WRC
City
Paris
Country
France
Deadline Paper
Start Date
End Date
Abstract

The 6th HiPEAC Workshop on Reconfigurable Computing 2012 &#8211; WRC 2012 provides a forum for researchers active in domains within the reconfigurable area&#046;<br>Its main focus is on reconfigurable architectures, tools and algorithm that facilitate such systems and applications tailored for reconfigurable platforms&#046;<br>The workshop intends to bring together both hardware designers and software developers that make extensive use of reconfigurable computing&#046; Moreover, it aims at enabling scientific discussion regarding future challenging issues&#046;<br>The main purpose of this workshop is to encourage the submission of work&#8211;in&#8211;progess in the topics covered by the call, thus providing quick and valuable feedback&#046;<br>The main purpose of this workshop is to encourage the submission of work&#8211;in&#8211;progess in the topics covered by the call, thus providing quick and valuable feedback&#046; As such we do not provide formal proceedigns&#046; We encoruage authors of papers who want to timestamp immediately their idea to forward their paper to HiPEAC tech&#8211;report, after presentation at our workshop&#046; Moreover, best papers will be selected and forwarded for possibile pubblication on Journal of Systems and Architectures &#8211; JSA&#046;<br>The topics of interest include, but are not limited to:<br>Reconfigurable Architectures:<br>&#8211; Novel architectures (logic blocks, interconnects, I/O)<br>&#8211; Reconfigurable fabrics combined with dedicated system blocks (DSP, processors, memory etc&#046;)<br>&#8211; Memory issues: adaptivity, coherence, latency tolerance, …<br>&#8211; Multicore support, resource sharing support, …<br>&#8211; Low power reconfigurable architectures, …<br>&#8211; Networks on chip tailored for reconfigurable architectures, …<br>&#8211; Dynamic and run&#8211;time reconfiguration,<br>&#8211; Defect and Fault Tolerance<br>Reconfigurable Tools and Technologies:<br>&#8211; System level design and HW/SW co&#8211;design<br>&#8211; Static and dynamic power efficiency<br>&#8211; Modeling, optimization, technology mapping and design verification<br>&#8211; Design and debug of reconfigurable systems<br>&#8211; Testing, verification and benchmarking<br>&#8211; Dedicated compilers and high&#8211;level languages<br>&#8211; Operating system support for reconfigurability<br>&#8211; Impact of reconfigurable hardware on real&#8211;time performance<br>Reconfigurable Applications and Algorithms:<br>&#8211; Adaptive and bio inspired applications<br>&#8211; Application domain specific, e&#046;g&#046; multimedia, bioinformatics, cryptography and more<br>&#8211; High&#8211;performance, high reliability and/or power efficient application acceleration<br>&#8211; Rapid prototyping<br>