Its main focus is on reconfigurable architectures, tools and algorithm that facilitate such systems and applications tailored for reconfigurable platforms. The workshop intends to bring together both hardware designers and software developers that make extensive use of reconfigurable computing. Moreover, it aims at enabling scientific discussion regarding future challenging issues. The main purpose of this workshop is to encourage the submission of work–in–progress in the topics covered by the call, thus providing quick and valuable feedback.<br>The topics of interest include, but are not limited to:<br>Reconfigurable Architectures:<br>– Novel architectures (logic blocks, interconnects, I/O)<br>– Reconfigurable fabrics combined with dedicated system blocks (DSP, processors, memory etc.)<br>– Memory issues: adaptivity, coherence, latency tolerance, …<br>– Multicore support, resource sharing support, …<br>– Low power reconfigurable architectures, …<br>– Networks on chip tailored for reconfigurable architectures, …<br>– Dynamic and run–time reconfiguration,<br>– Defect and Fault Tolerance<br>Reconfigurable Tools and Technologies:<br>– System level design and HW/SW co–design<br>– Static and dynamic power efficiency<br>– Modeling, optimization, technology mapping and design verification<br>– Design and debug of reconfigurable systems<br>– Testing, verification and benchmarking<br>– Dedicated compilers and high–level languages<br>– Operating system support for reconfigurability<br>– Impact of reconfigurable hardware on real–time performance<br>Reconfigurable Applications and Algorithms:<br>– Adaptive and bio inspired applications<br>– Application domain specific, e.g. multimedia, bioinformatics, cryptography and more<br>– High–performance, high reliability and/or power efficient application acceleration<br>– Rapid prototyping<br>
Abbrevation
HiPEAC
City
Paris
Country
France
Deadline Paper
Start Date
End Date
Abstract