5th IEEE International Workshop on Impact of Low Power Design on Test and Reliability, Annecy, Frankreich

The 5th IEEE International Workshop on Impact of Low Power Design on Test and Reliability<br>(LPonTR) aims to bring together design, reliability and test engineers and researchers to discuss<br>the impact of advanced low&#8211;power low&#8211;voltage design methodologies of nanometer silicon systems<br>on test and reliability&#046; Power and thermal issues, leakage, process variations, susceptibility to environmental<br>and operation&#8211;induced interference drive the development of low&#8211;power, process&#8211;tolerant<br>design techniques and generate a new set of test and reliability challenges, questing for an innovative<br>set of methodologies and tools&#046;<br>You are invited to participate in LPonTR’12 by presenting work that addresses current trends,<br>challenges and solutions in the following areas (but are not limited to):<br>• Energy&#8211;reliability tradeoff (inc&#046; controlled losses) and its integration with power management<br>• Power and Thermal Issues in 3D ICs<br>• Challenges of Ultra Lowpower design on test and reliability<br>• Emerging failure modes<br>• Test of SoC with power and thermal management<br>• Energy, power and process variations aware design and test<br>• Test and reliability implications of leakage<br>• Low&#8211;power/voltage DfT, Dynamic BIST, Scan and ATPG<br>• Delay, statistical and parametric testing for LP circuits<br>• Signal integrity under test<br>• Test and reliability of LP redundant systems<br>• Analog, mixed&#8211;signal and asynchronous low&#8211;power design, test and DfT<br>• EDA tools to support process&#8211;tolerant LP design<br>