<p class="MsoNormal" style="text–align: justify; line–height: normal; text–autospace: none; margin–bottom: .0001pt"> <span style="font–size:12.0pt;font–family:"Times New Roman","serif""> The 14th International Workshop of System Level Interconnect Prediction (SLIP) will be co–located with the 49th IEEE/ACM Design Automation Conference on June 3, 2012 at the Moscone Center, San Francisco, California. The general technical scope of the workshop is the design, analysis and prediction of interconnect and communication fabrics in electronic systems. The organizing committee invites original contributions to the workshop. These contributions include papers, tutorials, panels, and special sessions. Regular papers will be double blind reviewed. Submissions with author information will be rejected. We accept papers based on novelty and contributions. The accepted papers will be published in the proceedings of SLIP 2012, which will also be included in the ACM Digital Library. Note that ACM will hold the copyright for SLIP 2012 proceedings. Authors of accepted papers must sign an ACM copyright release form for their papers.</span></p> <p class="MsoNormal" style="text–align: justify; line–height: normal; text–autospace: none; margin–bottom: .0001pt"> <span style="font–size:12.0pt;font–family:"Times New Roman","serif""> </span></p> <p class="MsoNormal" style="line–height: normal; text–autospace: none; margin–bottom: .0001pt"> <b> <span style="font–size:12.0pt;font–family:"Times New Roman","serif""> Representative technical topics include, but are not limited to:</span></b></p> <p class="MsoNormal" style="line–height: normal; text–autospace: none; margin–bottom: .0001pt"> <span style="font–size: 12.0pt;font–family:"Times New Roman","serif"">1. Interconnect prediction <span style="color:black">and optimization</span><span style="color:#C00000"> </span>at various IC design stages</span></p> <p class="MsoNormal" style="line–height: normal; text–autospace: none; margin–bottom: .0001pt"> <span style="font–size: 12.0pt;font–family:"Times New Roman","serif"">2. Interconnect design challenges and system–level NoC design</span></p> <p class="MsoNormal" style="line–height: normal; text–autospace: none; margin–bottom: .0001pt"> <span style="font–size: 12.0pt;font–family:"Times New Roman","serif"">3. Design and analysis of power and clock networks</span></p> <p class="MsoNormal" style="line–height: normal; text–autospace: none; margin–bottom: .0001pt"> <span style="font–size: 12.0pt;font–family:"Times New Roman","serif"">4. Interconnect architecture of structural designs and FPGAs</span></p> <p class="MsoNormal" style="line–height: normal; text–autospace: none; margin–bottom: .0001pt"> <span style="font–size: 12.0pt;font–family:"Times New Roman","serif"">5. Interconnect fabrics of many–core architectures</span></p> <p class="MsoNormal" style="line–height: normal; text–autospace: none; margin–bottom: .0001pt"> <span style="font–size: 12.0pt;font–family:"Times New Roman","serif"">6. Design–for–manufacturing (DFM) techniques for interconnects</span></p> <p class="MsoNormal" style="line–height: normal; text–autospace: none; margin–bottom: .0001pt"> <span style="font–size: 12.0pt;font–family:"Times New Roman","serif"">7. High speed chip–to–chip interconnect design</span></p> <p class="MsoNormal" style="line–height: normal; text–autospace: none; margin–bottom: .0001pt"> <span style="font–size: 12.0pt;font–family:"Times New Roman","serif"">8. Design and analysis of chip–package interfaces</span></p> <p class="MsoNormal" style="line–height: normal; text–autospace: none; margin–bottom: .0001pt"> <span style="font–size: 12.0pt;font–family:"Times New Roman","serif"">9. Interconnect topologies of multiprocessor systems</span></p> <p class="MsoNormal" style="line–height: normal; text–autospace: none; margin–bottom: .0001pt"> <span style="font–size: 12.0pt;font–family:"Times New Roman","serif"">10. 3D interconnect design and prediction, including TSV architecture and monolithic 3D stacking</span></p> <p class="MsoNormal" style="line–height: normal; text–autospace: none; margin–bottom: .0001pt"> <span style="font–size: 12.0pt;font–family:"Times New Roman","serif"">11. Emerging interconnect technologies, e.g., RF interconnects, photonic networks, carbon–based interconnects, etc.</span></p> <p class="MsoNormal" style="line–height: normal; text–autospace: none; margin–bottom: .0001pt"> <span style="font–size: 12.0pt;font–family:"Times New Roman","serif"">12. Synergies between chip communication networks and networks arising in other contexts such as social networks, system biology, <span style="color:black">etc.</span></span></p> <p class="MsoNormal" style="line–height: normal; text–autospace: none; margin–bottom: .0001pt"> <span style="font–size: 12.0pt;font–family:"Times New Roman","serif""><br></span></p>
Abbrevation
SLIP
City
San Francisco
Country
United States
Deadline Paper
Start Date
End Date
Abstract