Design for Manufacturability and Yield, San Francisco, Vereinigte Staaten

Abbrevation

DFMY

Link

http://vlsicad.ucsd.edu/DFMY/

City

San Francisco

Country

United States

Deadline Paper

2012-04-01

Start Date

2012-06-04

End Date

2012-06-04

Abstract

Increased manufacturing susceptibility in todayâ€™s nanometer technologies requires up to date solutions for yield optimization. In fact, designing an SoC for manufacturability and yield aim at improving the manufacturing process and consequently its yield by enhancing communications across the design â€“ manufacturing interface. A wide range of Design–for– Manufacturability (DFM) and Design–for–Yield (DFY) and Design–for–Test (DFT) methodologies and tools are proposed today. Some of these are leveraged during the back–end design stages, and others have post design utilization, from lithography up to 3D integration, wafer sort, packaging, final test and failure analysis. These solutions can dramatically impact the business performance of chip manufacturers. They can also significantly affect age–old chip design flows. Using a DFM/DFY/DFT solution is an investment and thus choosing the most cost effective one(s) requires trade–off analysis. This workshop will cover practical case studies of successes and failures of DFM, DFY and DFT methodologies. Representative topics include, but are not limited to the following: Analog and Mixed–Signal DFM Test–Based Yield Learning Electrical, Design–Driven DFM Built–in Repair Analysis and Self–Repair Statistical Design Embedded Test and Diagnosis Variability Reduction Techniques Interconnect Variability OPC and RET 3D Integration System/Architecture Level Process Monitoring IP Adaptive Design Techniques in DFM/DFY Design–Aware Manufacturing Yield Enhancement IP Yield Management