Systems & Verification<br>Logic Design<br>Digital Implementation<br>Custom IC Design and RF Design<br>IC Packaging, SiP Design, and PCB Design<br>Manufacturability Signoff<br>Special Topics<br>Systems & Verification<br>• Power–aware functional verification and modelling<br>• Hardware/software co–verification<br>• Verification planning and management<br>• Specman–testbench automation<br>• Assertion–based verification/formal analysis<br>• Debug and analysis<br>• Analog/mixed–signal system verification<br>• Verification IP use and reuse<br>• In–circuit emulation/transaction–based acceleration<br>• SoC verification<br>• SystemVerilog/OVM testbench automation<br>• Transaction level modeling (TLM)<br>• UVM & OVM<br>• Virtual System Platform<br>Logic Design (will be considered part of the Unified Digital track)<br>• Modeling physical effects in logic synthesis<br>• Managing functional clock complexity<br>• Logical to physical design hierarchy strategies<br>• RTL synthesis<br>• Formal verification<br>• Low–power exploration/design/estimation in the front end<br>• Design for test/ATPG<br>• Timing constraint strategies and analysis<br>• Dealing with pre–mask ECOs<br>• New technology challenges<br>• IP assembly for SoC design<br>• High–performance design<br>Digital Implementation<br>• Low–power design implementation and analysis (MSV, PSO, biasing, CPF)<br>• Mixed–signal design implementation and analysis (A/d, D/a, A/D)<br>• What changes for designs at 45/32nm technology nodes (BULK, SOI and NVM processes)?<br>• Managing hierarchical design<br>• Hierarchical layout, chip assembly, prototyping, partitioning/budgeting, padring optimization, and associated ECOs<br>• Complex design planning and floorplanning<br>• Advanced techniques for block implementation and design closure<br>• Floorplanning, power, placement, CTS, optimisation, routing, and associated ECOs<br>• Timing and manufacturing variability implementation and analysis (statistical analysis, DFM–aware)<br>• Model–based vs. rule–based design implementation and analysis<br>• Lithography and CMP considerations<br>• Application of statistical methodologies in the design flow (timing, leakage, analysis, optimisation)<br>• Multi–mode/multi–corner analysis and optimisation techniques<br>• Managing the interdependencies of electrical signoff (timing, power and signal integrity, DFM–aware)<br>• Through silicon via (TSV) and stacked–die design and implementation<br>• Flip–chip design and implementation<br>• Library characterisation and modeling requirements for leading–edge design<br>• SiP considerations<br>• Advanced clocking strategies for managing power and variability<br>• Managing ECOs from RTL through physical implementation<br>Custom IC Design and RF Design<br>• Constraint–driven design and design/IP reuse<br>• RF and high–frequency design challenges<br>• Physical automation and optimisation<br>• New Virtuoso Space–Based Router and best practices<br>• Full custom floorplanning<br>• Physical verification<br>• Reliability<br>• Voltage drop/electromigration<br>• Thermal considerations<br>• Analog/mixed–signal design<br>• Behavioural modeling<br>• Mixed–mode, mixed–signal simulation and analysis<br>• Dealing with parasitics – design and verification<br>• IC 6.1.3 adoption, best practices, and customer experiences<br>• Modeling and characterisation<br>• Statistical simulation<br>• Circuit optimisation<br>• Verification planning<br>• Deep submicron challenges and solutions<br>• Library characterization, challenges, methodology, best practices<br>IC Packaging, SiP Design, and PCB Design<br>• Front–end design capture<br>• Schematic–less design entry<br>• Constraint–driven design<br>• Design partitioning and reuse<br>• Library and data management<br>• Integration with PLM systems<br>• Interactive and automatic routing<br>• Design for manufacturing and testability<br>• Signal and power integrity analysis<br>• Simulation model development<br>• Multi–gigahertz design<br>• Design automation and tool customisation<br>• Designing in DDR memories<br>• Silicon/package co–design<br>• Package–on–package design techniques and challenges<br>• High density interconnect (HDI) and flex designs<br>• ECAD/MCAD/thermal integration<br>• FPGA/PCB integration<br>• EMI reduction design techniques<br>• SiP and board I/O planning and design<br>Manufacturability Signoff<br>• Working with foundries<br>• Reliability modelling<br>• Design for test and manufacturing<br>• Signal integrity<br>• Yield optimisation (linking design and fab)<br>• DFY/DFM optimisation techniques and results<br>Special Topics<br>• Interoperability using OpenAccess<br>• Process design kit migration to IC 6.1 OpenAccess<br>• Process design kit automation and test<br>• Configuration management<br>• Tool interoperability and standards<br>• Chip–level integration and routing<br>• Design challenges in specific industry verticals such as automotive, wireless, entertainment, etc.<br>
Abbrevation
CDNLive! EMEA
City
Bangalore
Country
India
Deadline Paper
Start Date
End Date
Abstract