IEEE European Test Symposium, Avignon, Frankreich

Abbrevation

ETS

Link

http://www.lirmm.fr/ETS13

City

Avignon

Country

France

Deadline Paper

2012-12-03

Start Date

2013-05-27

End Date

2013-05-30

Abstract

The areas of interest include (but are not limited to) the following topics: – Analog Test – ATE Hardware and Software – Automatic Test Generation – Board Test and Diagnosis – Boundary Scan Test – Built–In Self Test (BIST) – Current–Based Test – Defect–Based Test – Delay and Performance Test – Dependability – Design for Test(ability) DfT – Design Verification and Validation – Diagnosis and Debug – Economics of Test – Failure Analysis – Fault Modeling and Simulation – Fault Tolerance – High–Speed I/0 Test – Low–Power IC Test – Memory Test and Repair – MEMS Test – Microprocessor Test – Mixed–Signal Test – Nanotechnology Test – On–line Test – Power Issues in Test – Reliability – RF Test – Self–Repair – Signal Integrity Test – Stacked IC Test – Standards in Test – System Test – System–in–Package (SiP) Test – System–on–Chip (SoC) Test – Soft Errors – Test(ability) Synthesis – Test of Reconfigurable Systems – Test Quality – Thermal Issues in Test – Transient and Soft Errors – Yield Analysis and Enhancement