10th ACM/IEEE Conference on Formal Methods and Models for Co-Design, Arlington, Vereinigte Staaten

Abbrevation

MEMOCODE

Link

http://www.cpe.vt.edu/reg/acmieee/index.html

City

Arlington

Country

United States

Deadline Paper

2012-03-16

Start Date

2012-07-16

End Date

2012-07-17

Abstract

The tenth MEMOCODE conference will attract researchers and practitioners who create methods, tools, and architectures for the design of hardware/software systems. These systems face increasing design complexity including tighter constraints on timing, power, costs, and reliability. MEMOCODE seeks submissions that present novel formal methods and design techniques addressing these issues to create, refine, and verify hardware/software systems. We also invite application–oriented papers, and especially encourage submissions that highlight the design perspective of formal methods and models, including success stories and demonstrations of hardware/software codesign. Furthermore, we invite poster presentations describing ongoing work with promising preliminary results. Topics of interest for regular submissions include but are not limited to – system and transaction–level modeling and verification, abstraction and refinement between different modeling levels, formal, semi–formal, and specification–driven verification, – design and verification methods for composition of concurrent systems: multi–core platform architectures, systems–on–chip, networks–on–chip, – formal methods and tools for hardware and software verification including theorem proving, decision procedures, – non–traditional and domain–specific design languages for hardware and software, novel models of computation, and new design paradigms that unify hardware and software design, – system–level estimation of performance and power in heterogeneous hardware/software architectures, – applications and demonstrators of formal design methodologies and case studies of innovative system–level design flows, – modeling and reuse of intellectual property at system–level, and design abstraction and high–level design demonstrating productivity and quality in generating and validating RTL and software.