Fith International Workshop on Network on Chip Architectures, VancouverB.C., Kanada

Abbrevation

NoCArc

Link

http://www.unikore.it/nocarc/index.html

City

VancouverB.C.

Country

Canada

Deadline Paper

2012-09-23

Start Date

2012-12-04

End Date

2012-12-05

Abstract

This workshop will focus on issues related to design, analysis and testing of on–chip networks. The topics of specific interest for the workshop include, but are not limited to: Topologies selection and synthesis for NoCs and MPSoCs Routing algorithms and router micro–architectures QoS in on–chip communication Mapping of cores to NoC slots Power and energy issues Fault tolerance and reliability issues Memory architectures for NoC Dynamic on–chip network reconfiguration Modeling and evaluation of on–chip networks On–chip interconnection network simulators and emulators Analytical analysis methods for NoC performance and other properties Verification, debug and test of NoC 3D NoC architectures Emerging technologies and new design paradigms Industrial case studies of SoC designs using the NoC paradigm Besides regular papers, papers describing work in progress or incomplete but sound new innovative ideas related to the workshop theme are also encouraged.