Papers are requested in the following areas<br>A pioneer and leading multidisciplinary conference, ISQED accepts and promotes papers related to the manufacturing, design and EDA. Authors are invited to submit papers in the various disciplines of high level design, circuit design (digital, analog, mixed–signal, RF), test & verification, design automation tools; processes; flows, device modeling, semiconductor technology, advance packaging, and biomedical & bioelectronic devices.<br>Electronic Design<br>System–level Design, Methodologies & Tools<br>FPGA Architecture, Design, and CAD<br>IC Package – Design Interactions & Co–Design<br>Advanced 3D ICs & 3D Packaging<br>Robust & Power–conscious Circuits & Systems<br>Emerging/Innovative Process & Device Technologies and Design Issues<br>Design of Reliable Circuits and Systems<br>Design of Embedded Systems<br>Design Automation and IP<br>IP Design, quality, interoperability and reuse<br>Design Verification and Design for Testability<br>Physical Design, Methodologies & Tools<br>EDA Methodologies, Tools, Flows<br>Manufacturing, Semiconductor Process and Devices<br>Design for Manufacturability/Yield & Quality<br>Effects of Technology on IC Design, Performance, Reliability, and Yield<br>The details of various topics of paper submission is as follows:<br>System–level Design, Methodologies & Tools (SDM)<br>Emerging system–level design paradigms, methods and tools aiming at quality. ESL design process and flow management. System–level design modeling, analysis, synthesis, estimation and verification for correct high–quality hardware/software systems. Development of reliable, responsive, secure, manufacturable, and defect–tolerant systems. New concepts, methods and tools addressing the hardware and system design complexity, multitude of aspects, manufacturability, and usage of technology information and manufacturing feedback in the system–, RTL– and logic level design. The influence of the nanometer technologies’ issues on the system–, RTL– and logic–level design. System–level trade–off analysis and multi–objective (yield, power, delay, area …) optimization. Effective and efficient development, implementation, analysis and validation of large SoCs integrating IP blocks from multiple vendors. Global, social, and economical implications of Electronic System and Design Quality. Emerging standards and regulations influencing system quality.<br>Package – Design Interactions & Co–Design (PDI)<br>Concurrent circuit, package, and PCB/PWB design and effect on quality. EDA tools and methodologies dealing with the IC Packaging electrical and thermal modeling and simulation for improved quality of product. SoC versus system in a package (SiP): design and technology solutions and tradeoffs; MCM, BGA, Flip Chip, 3D, TSV, and other innovative packaging techniques for various applications such as mixed–signal and RFIC.<br>Robust & Power–conscious Devices, Interconnects, and Circuits (PCC)<br>Power grid design, analysis and optimization; timing analysis and optimization; thermal analysis and design techniques for thermal management. Power–conscious design methodologies and tools; low power devices, circuits and systems; power–aware computing and communication; system–level power optimization and management. Design techniques for leakage current management.<br>Emerging/Innovative Process & Device Technologies and Design Issues (EDT)<br>Emerging processes & device technologies and implications on IC design with respect to design’s time to market, yield, reliability, and quality. Emerging issues in DSM CMOS: e.g. sub–threshold leakage, gate leakage, technology road mapping and technology extrapolation techniques. New and novel technologies such as SOI, Double–Gate (DG)–MOSFET, Gate–All–Around (GAA)–MOSFET, Vertical–MOSFET, strained CMOS, high–bandwidth metallization, 3D integrated circuits, nanodevices, etc.<br>Design of Reliable Circuits and Systems (DFR)<br>Device and process reliability issues and effect on design of reliable circuits and systems. ESD design for digital, mixed signal and RF applications. Exploration of critical factors such as noise, substrate coupling, cross–talk and power supply noise. Significance and trends in process reliability effects such as gate oxide integrity, electromigration, ESD, etc., and their relation to electronic design.<br>EDA Methodologies, Tools, Flows & IP Cores; Interoperability and Reuse (EDA)<br>EDA tools addressing design for manufacturing, yield, and reliability. Management of design process, design flows and design databases. EDA tools interoperability issues and implications. Effect of emerging technologies, processes & devices on design flows, tools, and tool interoperability. Emerging EDA standards. EDA design methodologies and tools that address issues which impact the quality of the realization of designs into physical integrated circuits. IP modeling and abstraction. Design and maintenance of technology independent hard and soft IP blocks. Methods and tools for analysis, comparison and qualification of libraries and hard IP blocks. Challenges and solutions of the integration, testing, qualifying, and manufacturing of IP blocks from multiple vendors. Third party testing of IP blocks. Risk management of IP reuse. IP authoring tools and methodologies.<br>Design Verification and Design for Testability (DVFT)<br>Hardware and Software, Formal and simulation based design verification techniques to ensure the functional correctness of hardware early in the design cycle. DFT and BIST for digital and SoC. DFT for analog/mixed–signal ICs and systems–on–chip, DFT/BIST for memories. Test synthesis and synthesis for testability. DFT economics, DFT case studies. DFT and ATE. Fault diagnosis, IDDQ test, novel test methods, effectiveness of test methods, fault models and ATPG, and DPPM prediction. SoC/IP testing strategies. Design methodologies dealing with the link between testability and manufacturing.<br>Physical Design, Methodologies & Tools (PDM)<br>Physical design for manufacturing; Physical synthesis flows for correct–by–construction quality silicon, implementation of large SoC designs. Tool frameworks and data–models for tightly integrated incremental synthesis, placement, routing, timing analysis and verification. Placement, optimization, and routing techniques for noise sensitivity reduction and fixing. Algorithms and flows for harnessing crosstalk–delay during physical synthesis. Tool flows and techniques for antenna rule and electromigration rule avoidance and fixing. Spare–cell strategies for ECO, decoupling capacitance and antenna rule fixing. Physical planning tools for predictable power–aware circuits. Reliable clock tree generation and clock distribution methodologies for Gigahertz designs. EDA tools, design techniques, and methodologies, dealing with issues such as: timing closure, R, L, C extraction, ground/Vdd bounce, signal noise/cross–talk /substrate noise, voltage drop, power rail integrity, electromigration, hot carriers, EOS/ESD, plasma induced damage and other yield limiting effects, high frequency effects, thermal effects, power estimation, EMI/EMC, proximity correction & phase shift methods, verification (layout, circuit, function, etc.).<br>Design for Manufacturability/Yield & Quality (DFQ)<br>DFM/DFY/DFQ definitions, methodologies, matrices, and standards. Quality–based design methodologies and flows for custom, semi–custom, ASIC, FPGA, RF, memory, networking circuit, etc. Design flows and methodologies for SoC, and SiP. Analysis, modeling, and abstraction of manufacturing process parameters and effects for highly predictable silicon performance. Design and synthesis of ICs considering factors such as: signal integrity, transmission line effects, OPC, phase shifting, and sub–wavelength lithography, manufacturing yield and technology capability. Design for diagnosability, defect detection and tolerance; self–diagnosis, calibration and repair. Design and manufacturability issues for digital, analog, mixed signal, RF, MEMS, opto–electronic, biochemical–electronic, and nanotechnology based ICs. Redundency and other yield improving techniques. Global, social, and economic implications of design quality. Mask making methods and advances impacting manufacturability and yield.<br>Submission of Papers<br>Authors should submit FULL–LENGTH, original, unpublished papers (Minimum 4, maximum 8 pages). To permit a blind review, do not include name(s) or affiliation(s) of the author(s) on the manuscript and abstract. Submit your papers using the on–line paper submission procedure available in the ISQED web site. Please check the as–printed appearance of your paper before submitting the paper. The guidelines for the paper format is provided in this website (see below). Use the on–line paper submission procedure by clicking the following link: ON–LINE. If you have problem accessing the paper submission site it is located at: https://www.softconf.com/d/isqed2013<br>Submission of Workshop/Tutorial Proposals<br>Several workshop/tutorial sessions will be held on the first day, and would offer valuable opportunities for practicing professionals to refresh or upgrade their skills in quality–based IC design techniques, methodologies and tools. These sessions are intended to supplement the conference by providing in depth, practical and proven design solutions. Workshops/Tutorials will be taught by experts in the field, who are intimately involved with the issues and solutions in their perspective areas, from both the industry and academia. If interested in offering tutorial, please send your tutorial proposals to the ISQED workshop/tutorial committee to isqed2013@ISQED.org<br>The proposal should include:<br>Title of Workshop/Tutorial<br>Name of organizer<br>Name(s), address, and affiliation of the Moderator<br>Name(s), address, and affiliation of presenter(s)<br>Half–page summary of each presenter′s biography<br>
Abbrevation
ISQED
City
Santa Clara
Country
United States
Deadline Paper
Start Date
End Date
Abstract