7th International Workshop on Interconnection Network Architectures: On-Chip, Multi-Chip, Berlin, Deutschland

Abbrevation

INA-OCMC

Link

http://mpsoc.unife.it/~inaocmc/

City

Berlin

Country

Germany

Deadline Paper

2012-10-19

Start Date

2013-01-23

End Date

2013-01-23

Abstract

When interconnecting different end–nodes in on–chip and multi–chip processing architectures, the communication infrastructure plays a dominant role in determining overall system metrics such as performance, reliability and often even area and power. On the other hand, each application domain poses its own design constraints that the interconnect fabric has to cope with, thus leading to well differentiated architecture design principles. Ultimately, careful engineering of the interconnection network is at the core of the successful development of both on–chip and multi–chip processing architectures. The program of the workshop is organized around two main directions. The first direction includes original papers describing new and previously unpublished results on all aspects of interconnection network architectures. Topics of interest include but are not limited to: * Networks–on–Chip (NoC) * Multi–Chip Interconnection Networks, including Cluster Interconnects * "Commodity Switches" as general–purpose building blocks * Switching, buffering, and routing architectures * Flow control and congestion management in switching fabrics * Virtualization * Topology exploration * Timing, synchronous/asynchronous communication * Reliability, availability, fault tolerance * Area/power versus functionality/QoS support in NoC architectures * NoC physical link design * NoC testing and verification * Programming models for NoC–centric systems The second direction will be focused to the design and analysis of reconfigurable Networks–on–Chip. Besides of the already known, hardwired interconnection networks, this special session tries to identify possible new solutions to the area of reconfigurable Networks–on–Chip that can better adapt to system′s needs. The main target of this session is to attract highly qualified submissions that fall into the next three broad categories: * Specifically designed network components that allow some form of static or runtime programmability to their function, allowing for higher performance under certain occasions or for additional fault tolerance. * The mapping and implementation of NoCs to reconfigurable platforms (FPGAs) as soft components and the implications that this mapping generates to the NoC architecture. * On–demand network topologies and structures that better fit to the application characteristics and algorithms.