<span class="Apple–style–span" style="border–collapse: separate; color: rgb(0, 0, 0); font–family: ′Times New Roman′; font–style: normal; font–variant: normal; font–weight: normal; letter–spacing: normal; line–height: normal; orphans: 2; text–align: –webkit–auto; text–indent: 0px; text–transform: none; white–space: normal; widows: 2; word–spacing: 0px; –webkit–border–horizontal–spacing: 0px; –webkit–border–vertical–spacing: 0px; –webkit–text–decorations–in–effect: none; –webkit–text–size–adjust: auto; –webkit–text–stroke–width: 0px; font–size: medium; "><span class="Apple–style–span" style="color: rgb(17, 17, 17); font–family: verdana, arial, helvetica, sans–serif; font–size: 13px; text–align: –webkit–left; ">The International Symposium on Asynchronous Circuits and Systems (ASYNC) is the premier forum for researchers to present their latest findings in the area of asynchronous design. The 2013 symposium will be held in Santa Monica, California.<span class="Apple–converted–space"> </span><br>Authors are invited to submit full papers on any aspect of asynchronous design, ranging from the core topics of design, synthesis, and test, to asynchronous applications in system–level integration and emerging computing technologies. Topics of interest include, but are not limited to:<span class="Apple–converted–space"> </span><br>Mixed–timed circuits, GALS systems, Network–on–Chip, and multi–chip interconnects<span class="Apple–converted–space"> </span><br>Elastic and latency–tolerant synchronous design<span class="Apple–converted–space"> </span><br>Synchronization, clock domain crossing, arbitration, and metastability<span class="Apple–converted–space"> </span><br>Asynchronous pipelines, architectures, CPUs, and memories<span class="Apple–converted–space"> </span><br>Asynchronous ultra–low power systems, energy harvesting, and mixed–signal/analogue<span class="Apple–converted–space"> </span><br>Asynchrony in emerging technologies, including bio, neural, nano and quantum computing<span class="Apple–converted–space"> </span><br>CAD tools for asynchronous design, synthesis, analysis, and optimization<span class="Apple–converted–space"> </span><br>Formal methods for verification and performance/power analysis<span class="Apple–converted–space"> </span><br>Test, security, and fault tolerance<span class="Apple–converted–space"> </span><br>Asynchronous variability–tolerant design and design for manufacturing<span class="Apple–converted–space"> </span><br>Circuit designs, case studies, comparisons, and applications<span class="Apple–converted–space"><br></span></span></span>
Abbrevation
ASYNC
City
Santa Monica
Country
United States
Deadline Paper
Start Date
End Date
Abstract