The growing complexity and shrinking geometries of modern device technologies are making high–density, low–voltage devices increasingly susceptible to the influences of electrical noise, process variation, transistor aging, and the effects of natural radiation. The system–level impact of these errors can be far–reaching. Growing concern about intermittent errors, unstable storage cells, and the effects of aging are influencing system design. This workshop provides a forum for discussing current research and practice in system–level error management. Participants from industry and academia explore both current technologies and future research directions (including nanotechnology). We are soliciting papers that address the system–level effects of errors from a variety of perspectives: architectural, logical, circuit–level, and semiconductor processes. Case studies are also solicited. <p>Key areas of interest are (but not limited to):</p> <ul><li>Technology trends and the impact on error rates </li><li>New error mitigation techniques </li><li>Characterizing the overhead and design complexity of error mitigation techniques </li><li>Case studies describing the engineering tradeoffs necessary to decide what mitigation technique to apply </li><li>Experimental data </li><li>System–level models: derating factors and validation of error models </li><li>Error handling protocols (higher–level protocols for robust system design)</li></ul><p><br></p>
Abbrevation
SELSE
City
Stanfort
Country
United States
Deadline Paper
Start Date
End Date
Abstract