The International Symposium on Networks–on–Chip (NOCS) is the premier event dedicated to interdisciplinary research on on–chip and chip–scale communication technology, architecture, design methods, applications and systems. NOCS brings together scientists and engineers working on NoC innovations and applications from inter–related research communities, including computer architecture, networking, circuits and systems, embedded systems, and design automation. Topics of interest include, but are not limited to:<br>NoC Architecture and Implementation:<br>Network architecture (topology, routing, arbitration)<br>NoC Quality of Service<br>Timing, synchronous/asynchronous communication<br>NoC reliability issues<br>Network interface issues<br>NoC design methodologies and tools<br>Signaling & circuit design for NoC links<br>Physical design of interconnect & NoC<br>NoC Application:<br>Mapping of applications onto NoCs<br>NoC case studies, application–specific NoC design<br>NoCs for FPGAs, structured ASICs, CMPs and MPSoCs<br>NoC designs for heterogeneous systems, fused CPU–GPU architectures, etc<br>Network design for 2.5D & 3D stacked logic and memory<br>NoC Analysis and Verification:<br>Power, energy & thermal issues (at the NoC, un–core and/or system–level)<br>Benchmarking & experience with real NoC–based hardware<br>Modeling, simulation, and synthesis of NoCs<br>Verification, debug & test of NoCs<br>Metrics and benchmarks for NoCs<br>NoC at the un–core and system–level:<br>Design of memory subsystem (un–core) including memory controllers, caches, cache coherence protocols & NoCs<br>NoC support for memory and cache access<br>OS support for NoCs<br>Programming models including shared memory, message passing and novel programming models<br>Multi/many–core workload characterization & evaluation<br>Optical, RF, & emerging technologies for on–chip/inpackage interconnects Issues related to large–scale systems (datacenters, supercomputers) with NoC–based systems as building blocks<br>
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NOCS
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United States
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