Symposium on VLSI Circuits, Kyoto, Japan

Abbrevation

VLSI Circuits

Link

http://www.vlsisymposium.org/

City

Kyoto

Country

Japan

Deadline Paper

2013-01-21

Start Date

2013-06-11

End Date

2013-06-13

Abstract

The 2013 Symposium on VLSI Circuits will provide designers of integrated circuits an opportunity to meet and present important new works on all aspects of VLSI circuits. The 013 Symposium on VLSI Technology (please see the reverse side) will be held at the same location with two days of overlap. A single registration allows participants to attend both of the Symposia, and offers unique opportunities to interact and synergize on topics of joint interest. The scope of the Symposium on VLSI Circuits includes innovations and advances in following areas. Special focus will be placed on VLSI systems and solutions for smarter society. – RF and wireless communication circuits and architecture, including CMOS RF and mm–wave, and digital implementations – Wireline transceiver and I/O design, spanning chip–to–chip to long–reach applications – Digital VLSI circuits and system techniques for processor, memory, and complex SOC architectures and implementations – Clock generation and distribution for high frequency digital and mixed–signal applications – Analog and mixed signal circuits such as data converters, PLL, amplifiers, filters, and sensing FE – Memory circuits and architectures for SRAM, DRAM, and non–volatile, including emerging memories – Power management technologies, including circuits for voltage regulators and voltage references, VLSI systems for battery management, power saving, energy harvesting, and renewable energy – Application oriented circuits and VLSI systems, including biomedical and healthcare, electric vehicles, power grids, and sensor networks JOINT CIRCUITS AND TECHNOLOGY FOCUS SESSIONS Joint circuit and technology focus sessions will be offered in the following special topics of joint interest. Paper submissions highlighting major innovations and advances in circuits, designs, tools and methodologies in these areas are strongly encouraged. The scope includes, but is not limited to the following area: â€¢ Design in scaled technologies: scaling of analog and mixed–signal design based on novel device and interconnect materials and structures â€¢ Design enablement: design for manufacturing and robustness, process–design co–optimization for ultra–low voltage and power, on–die measurement and monitoring of variability and reliability â€¢ Memory technology and design: embedded and stand–alone SRAM, DRAM, Flash, PCRAM, RRAM, MRAM, etc. â€¢ 3D (TSV) and heterogeneous integration: power and thermal management, inter–chip communication, SiP architectures and applications. Papers will be considered on the basis of originality, innovation and advancing the field. Implementation in silicon and measured results will be considered favorably in the ratings.