Memory continues to be a major bottleneck in almost all computing systems.<br>It is becoming more so as more cores and agents are sharing parts of the<br>memory system and as applications that run on the cores are becoming<br>increasingly data intensive. Continuing the tradition of seven previous<br>successful incarnations, MSPC 2013 will provide a forum for publishing<br>and discussing all aspects of memory performance and correctness on<br>a variety of systems (multi–core, desktop, embedded, server/cloud,<br>high–performance computing, sensor, etc) and related software and<br>hardware innovations at various levels of the technology stack. We<br>invite new submissions that tackle issues in memory system<br>performance, efficiency, correctness, and dependability in<br>both hardware and software layers. Example areas of interest<br>include but are not limited to the following:<br>* Hardware, software, and hybrid techniques for better memory<br>performance, correctness, reliability, efficiency<br>* Memory hierarchy design for chip multiprocessors (CMPs)<br>* Emerging memory technologies (e.g., Phase Change Memory, MRAM)<br>* Characterization and analysis of memory systems performance<br>* Insightful experimental evaluation and analysis of memory–intensive<br>workloads<br>* Static and dynamic techniques for understanding and improving memory<br>performance and efficiency<br>* Managed memory and garbage collection optimizations<br>* Hardware and software techniques for ensuring memory safety and<br>detecting memory–related bugs<br>* Hardware and software memory models and their impact on<br>programmability and performance<br>* Memory system issues in accelerator–based computing (e.g., GPGPU)<br>* Memory system issues in embedded computers and tiny devices<br>* Prefetching, compression, latency tolerance techniques for memory<br>* Memory power and energy management techniques<br>* Memory reliability management techniques<br>
Abbrevation
MSPC
City
SeattleWA
Country
United States
Deadline Paper
Start Date
End Date
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