It is a pleasure to invite you to submit your Original Research Paper in "27th International Conference on VLSI Design and also in the Concurrently run 13th International Conference on Embedded Systems" to be held in Indian Institute of Technology Bombay, Mumbai, India from 5th January to 9th January 2014. The Conference is sponsored by VLSI Society of India and Technically sponsored by IEEE. The Conference proceeding will be published in soft form only. All accepted papers will be accessible through IEEE Explore system. The topics of Conference′s interest are all aspects of VLSI Design and Embedded systems.<br>1. Embedded Systems<br>Embedded system hardware/software co–design; Reconfigurable hardware design; Embedded software; Real–time operating systems; Middleware and virtualization; Embedded multi–cores and many–cores; Communications; Encryption, security, compression; Hybrid systems–on–chip; Sensor networks; Programmable devices; Hardware–software co–verification; Embedded system reliability; Embedded applications (automotive, mobile, medical, etc.), platforms, and case studies<br>2. Digital Design<br>Low–power design; Asynchronous design; Package and board design<br>3. Analog/RF Design<br>Low–power design; Analog, mixed–signal, and RF systems; Package and board design<br>4. System–level Design/ESL<br>System–level design methodology; Gigascale design methodology; Multicore systems; Processor and memory design; Concurrent interconnect; Networks–on–chip; Defect tolerant architectures<br>5. Logic Synthesis and Physical Design<br>Logic synthesis; Technology mapping; Asynchronous synthesis; Physical design; Floor planning; Placement; Routing; Clock Design; Layout issues in design for manufacturability<br>6. Test and Reliability<br>Fault modeling/simulation; ATPG; DFT; Delay test; Fault–tolerance; Online test; AMS/RF test; Board–level and system–level test; Silicon debug, post–silicon validation; Memory test; Reliability test<br>7. Functional Verification<br>Behavioral Simulation; RTL Simulation; Coverage Driven Verification; Assertion Based Verification; Gate–level simulation; Emulation; Hardware Assisted Verification; Formal Verification; Equivalence Checking; Verification Methodologies<br>8.Device/circuit simulation and modeling<br>Design verification; Signal integrity; Technology modeling–design–simulation; Analog/mixed–signal simulation; Multi–domain simulation; Numerical methods; Device modeling; Timing analysis; Asynchronous timing; Device/circuit level variability models; Reliability simulation<br>9.Emerging Technologies<br>
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Mumbai
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India
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