Abbrevation
SOC
City
Irvine
Country
United States
Start Date
End Date
Abstract

“As the industry continues its relentless drive to smaller and smaller geometries, deep technology understanding and strategic business engagements are required to deliver the innovative and complex System&#8211;on&#8211;Chip (SoC) solutions to a demanding market,” said Professor Michael Green, Chairman of Department of Electrical Engineering and Computer Science, University of California, Irvine&#046; “The annual International System&#8211;on&#8211;Chip (SoC) Conferences have been an outstanding forum to gather the leading&#8211;edge technologies and products from industry leaders and highly&#8211;recognized academia into a two&#8211;day SoC Conference for those who are involved in designing complex ICs and IPs, researchers, semiconductor and EDA technologists, analysts, and students across the world&#046;”<br>The SoC Conference Technical Advisory Board and Organizing Committee are seeking submissions on all aspects of Chip Design and Development, Semiconductor Technology, Mixed&#8211;Signal design, FPGA Solutions, ASSP, ASIC, Analog Design Techniques, High&#8211;Speed Interfaces and Challenges, CPU/DSP/MCU Cores, Leading&#8211;Edge IPs, Network&#8211;on&#8211;Chip (NoC), Leading 14 nm Foundries and Designs, Sub 10 nm Design Challenges, SOI Possibilities, Understanding FinFETs, IP Design and Development, IP Reusability, Design for Testing (DFT), Design for Manufacturing (DFM), Chip Design and Verification, 3D&#8211;Packaging, Low&#8211;Power Design Techniques, EDA Tools and Solutions for complex SoC Platforms, EDA Tools for Analog and Mixed&#8211;Signal Designs, New Design Methodologies and Approaches, Technology and Business Challenges, and much more&#046;<br>