The "power wall" has forced chip designers and system architects to<br>integrate novel power and thermal management control loops into<br>systems to enable smaller margins between nominal and worst–case<br>operating points. These management protocols create new challenges for<br>chip and system designers. Examples include control loop stability,<br>robustness of the management protocols, potential security<br>vulnerabilities in integrated control loops and management firmware,<br>and system security and safety challenges triggered by violations of<br>energy, reliability, power or thermal limits.<br>We have coined the term "robust and energy–secure systems" to cover<br>the broad range of research being pursued within industry and academia<br>to ensure reliable and secure operation of systems with integrated<br>power, reliability, and thermal management control loops.<br>Through this JETCAS special issue, we seek novel research papers on<br>holistic approaches to designing emerging on–chip control systems.<br>We solicit papers in the areas of energy/power/thermal management,<br>reliability, and security to provide a comprehensive view of the<br>hardware and software aspects of Robust and Energy–Secure Systems.<br>Areas of interest include, but are not limited to:<br>– Holistic cross–layer energy, power, thermal and reliability<br>–management solutions<br>– Robustness of system energy/power/thermal/reliability management:<br>– verification, validation and design for verification<br>– Reliability and security holes exposed by energy/power/thermal<br>– management protocols<br>– Guarded, two–level management protocols for safety, security and<br>– low verification complexity<br>– Architectural implications of and system software support for<br>– robust energy/power/thermal management<br>– Reliability and security issues in emerging low–power memory<br>– technologies<br>– Power– and thermal–based side–channel attacks<br>
Abbrevation
Robust and Energy-Secure Systems
Country
NN
Deadline Paper
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