<p class="MsoNormal"><span style="font–size: 10.0pt;font–family: Arial , sans–serif;">Topics of interest include but are not limited to:</span></p><p class="MsoNormal"><span style="font–size: 10.0pt;font–family: Arial , sans–serif;"> </span></p><p class="MsoNormal"><span style="font–size: 10.0pt;font–family: Arial , sans–serif;">– Analog Mixed Signal Test</span></p><p class="MsoNormal"><span style="font–size: 10.0pt;font–family: Arial , sans–serif;">– Automatic Test Generation</span></p><p class="MsoNormal"><span style="font–size: 10.0pt;font–family: Arial , sans–serif;">– Built–In Self–Test</span></p><p class="MsoNormal"><span style="font–size: 10.0pt;font–family: Arial , sans–serif;">– Defect–Based Test</span></p><p class="MsoNormal"><span style="font–size: 10.0pt;font–family: Arial , sans–serif;">– Design and Synthesis for Testability</span></p><p class="MsoNormal"><span style="font–size: 10.0pt;font–family: Arial , sans–serif;">– Design for Electromagnetic Compatibility</span></p><p class="MsoNormal"><span style="font–size: 10.0pt;font–family: Arial , sans–serif;">– Design for Reliable Embedded Software</span></p><p class="MsoNormal"><span style="font–size: 10.0pt;font–family: Arial , sans–serif;">– Design Verification/Validation</span></p><p class="MsoNormal"><span style="font–size: 10.0pt;font–family: Arial , sans–serif;">– Economics of Test</span></p><p class="MsoNormal"><span style="font–size: 10.0pt;font–family: Arial , sans–serif;">– Fault Analysis and Diagnosis</span></p><p class="MsoNormal"><span style="font–size: 10.0pt;font–family: Arial , sans–serif;">– Fault Modeling and Simulation</span></p><p class="MsoNormal"><span style="font–size: 10.0pt;font–family: Arial , sans–serif;">– Fault–Tolerance in HW/SW</span></p><p class="MsoNormal"><span style="font–size: 10.0pt;font–family: Arial , sans–serif;">– Fault–Tolerant Architectures</span></p><p class="MsoNormal"><span style="font–size: 10.0pt;font–family: Arial , sans–serif;">– Memory Test and Repair</span></p><p class="MsoNormal"><span style="font–size: 10.0pt;font–family: Arial , sans–serif;">– On–Line Testing</span></p><p class="MsoNormal"><span style="font–size: 10.0pt;font–family: Arial , sans–serif;">– Process Control and Measurements</span></p><p class="MsoNormal"><span style="font–size: 10.0pt;font–family: Arial , sans–serif;">– Radiation/EMI</span></p><p class="MsoNormal"><span style="font–size: 10.0pt;font–family: Arial , sans–serif;">– Hardening Techniques</span></p><p class="MsoNormal"><span style="font–size: 10.0pt;font–family: Arial , sans–serif;">– Software Fault–Tolerance</span></p><p class="MsoNormal"><span style="font–size: 10.0pt;font–family: Arial , sans–serif;">– Software On–Line Testing</span></p><p class="MsoNormal"><span style="font–size: 10.0pt;font–family: Arial , sans–serif;">– System–on–Chip Test</span></p><p class="MsoNormal"><span style="font–size: 10.0pt;font–family: Arial , sans–serif;">– Test Resource Partitioning</span></p><p class="MsoNormal"><span style="font–size: 10.0pt;font–family: Arial , sans–serif;">– Timing Analysis for Critical Applications</span></p><p class="MsoNormal"><span style="font–size: 10.0pt;font–family: Arial , sans–serif;">– WCET Estimation</span></p><span style="font–size: 10.0pt;font–family: Arial , sans–serif;">– Yield Optimization</span>
Abbrevation
LATW
City
Fortaleza
Country
Brazil
Deadline Paper
Start Date
End Date
Abstract