SEMICON, Seoul, Südkorea | edacentrum 3.0

Link

http://www.semiconkorea.org/en/Programs/CallforPapers

City

Seoul

Country

South Korea

Deadline Paper

2013-10-11

Start Date

2014-02-12

End Date

2014-02-14

Abstract

The SEMI Technology Symposium (STS) 2014, which held in conjunction with SEMICON Korea 2014 provides a dynamic spectrum of technology direction for semiconductor manufacturing in the next generation from a wide variety of aspects. The symposium will cover the latest technologies topics: Advanced Lithography, Interconnection & Advanced Process, Device, Plasma Science and Etching, Contamination–free Manufacturing and CMP Technology, Electropackage System and Interconnect Product. Every year, STS focuses specifically on suggesting semiconductor industryâ€™s future and recent technology trends. Your participation will enhance the value of STS and provide with valuable contents to semiconductor industry people. SEMI welcomes industry input and suggestions from potential speakers. SEMI is soliciting technical papers related to any of the following topics; S1. Advanced Lithography – Resist Processes and Materials – Photomask Processes and Materials – Lithography Simulation (Wafer/Mask Processes), OPC and Design for Manufacturing – Imaging Fundamentals and Resolution Enhancement Methods – Immersion Lithography and various extension techniques – Multiple Exposure and Double Patterning Techniques – Advanced Metrology Technology for Wafer and Mask – Extreme Ultraviolet Lithography – Directed Self Assembly – Alternative Lithography (E–beam, Nano–Imprint, Maskless Lithography, and others) – Application of Lithography to Nanotechnology S2. Interconnection & Advanced Process Technology – Advanced Gapfill Technology – Interconnection (Cu, Al, W Barrier Metal, Gate Electrode, Salicidation, Optical Interconnection) – Dielectric (high k, low k, Gate Dielectric, Ferroelectric, Passivation) – Doping & Heat Treatment Process (I2p, Plasma Doping, GILD, SADS, RTP, Furnace, Damage – Control) – Epitaxial Growth (Blanket, Selective, Device Integration) – SOI Materials & Processes (Wafer Manufacturing, Device Manufacturing) – Materials and Process for Non Volatile Memory Devices (PCRAM, STT–RAM, ReRAM, PoRAM, etc) – Nano Process Technology (Quantum Dot/Nanowire/Layer Formation) S3. Device Technology – Advanced CMOS Technology – Advanced Memory Technology – Emerging Memory Technology – Beyond CMOS Technology – SoC Technology – Process/Device/Interconnection Modeling & Reliability – Power Devices S4. Plasma Science and Etching Technology – Etch Processes related to Gate, HARC, and TSV – New Etch Tools – Plasma Technology – Gate & 3–D Etch Processing – New & Novel Material Etch (MRAM, New Mask, New Material, ReRAM, etc.) – New Etch Tools for Next Generation – HARC & Low–k Etch – TSV Issues – New Plasma Etch Technologies (New Plasma Sources, Pulsing, etc.) – Plasma & Process Diagnostics – Plasma related Simulation S5. Contamination–Free Manufacturing and CMP Technology – Advanced Wet/Dry Surface Preparation in FEOL/BEOL – Environmentally Benign Manufacturing/PFC Emission Reduction – Micro–, Nano–contamination Control – Damage/Loss Free Nano Particle Removal – Yield Enhancement Technology – Advances in CMP, Related Processes and Equipments – CMP Consumables and Metrology – Scratch Reduction/Mechanism – CMP Modeling and Simulation – Post CMP Cleaning S6. Electropackage System and Interconnect Product – TSV Product Planning – TSV Reliability and Quality – TSV Supply Chain Management – TSV MI (Measurement and Instrumentation) – TSV Temporary Bonding/Debonding and Handing – TSV Backside Processing and Bumping – TSV Bonding and Stacking – TSV Design