System Level Interconnect Prediction, San Francisco, Vereinigte Staaten

The general technical scope of the workshop is the design, analysis, prediction, and optimization of interconnect and communication fabrics in electronic systems&#046; The organizing committee invites original contributions to the workshop&#046; These contributions include papers, tutorials, panels, special sessions, and posters&#046; We accept papers based on novelty and contributions to the advancement of the field&#046; The accepted papers will be published in the ACM and IEEE digital libraries&#046; The special focus topic is 3D interconnects; papers that target this topic are highly encouraged&#046; Selected papers will be invited as a special section or issue in a leading ACM or IEEE journal or magazine&#046;<br>Technical topics include but are not limited to:<br>1&#046; Interconnect prediction and optimization at various IC design stages<br>2&#046; Interconnect design challenges and system‐level design for FPGAs and NOCs<br>3&#046; Design, analysis, and optimization of power and clock networks<br>4&#046; Interconnect reliability<br>5&#046; Interconnect topologies and fabrics of multi‐ and many‐core architectures<br>6&#046; Design‐for‐manufacturing (DFM) and yield techniques for interconnects<br>7&#046; High speed chip‐to‐chip interconnect design<br>8&#046; Design and analysis of chip‐package interfaces<br>9&#046; Power consumption of interconnects<br>10&#046; 3D interconnect design and prediction<br>11&#046; Emerging interconnect technologies<br>12&#046; Applications of interconnects to social, genetic, and biological systems<br>13&#046; Co‐optimization of interconnect technology and chip design<br>