Abbrevation
ICCAD
City
San Jose
Country
United States
Deadline Paper
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Abstract

<p><span class="c7"><strong>ICCAD serves EDA and design professionals, highlighting new challenges and innovative solutions for Integrated Circuit Design Technologies and Systems&#046; ICCAD covers the full range of CAD topics – from device and circuit&#8211;level CAD up through system&#8211;level CAD and embedded software, as well as CAD for post&#8211;CMOS design and novel application areas, such as biology and nanotechnology&#046;</strong></span></p><p><span class="c7"><strong>1) SYSTEM&#8211;LEVEL </strong><strong>CAD</strong></span><br><strong>1</strong><strong>&#046;1 System Design:</strong></p> <ul><li><span style="line&#8211;height: 1&#046;5;">System&#8211;level specification, modeling, and </span><span style="line&#8211;height: 1&#046;5;">simulation</span></li><li><span style="line&#8211;height: 1&#046;5;">System design flows and methods</span></li><li><span style="line&#8211;height: 1&#046;5;">HW/SW co&#8211;design, co&#8211;simulation,</span><span style="line&#8211;height: 1&#046;5;">co&#8211;optimization, and co&#8211;exploration</span></li><li><span style="line&#8211;height: 1&#046;5;">HW/SW platforms</span></li><li><span style="line&#8211;height: 1&#046;5;">Rapid prototyping</span></li><li><span style="line&#8211;height: 1&#046;5;">System design case studies and applications</span></li><li><span style="line&#8211;height: 1&#046;5;">System&#8211;level issues for 3D integration</span></li><li><span style="line&#8211;height: 1&#046;5;">Micro&#8211;architectural transformation</span></li><li><span style="line&#8211;height: 1&#046;5;">Memory architecture and system synthesis</span></li><li><span style="line&#8211;height: 1&#046;5;">System communication architecture</span></li><li><span style="line&#8211;height: 1&#046;5;">Network&#8211;on&#8211;chip design methodologies </span><span style="line&#8211;height: 1&#046;5;">and CAD</span></li><li><span style="line&#8211;height: 1&#046;5;">Network&#8211;on&#8211;chip design case studies </span><span style="line&#8211;height: 1&#046;5;">and prototyping</span></li></ul><p><strong style="line&#8211;height: 1&#046;5;">1&#046;2</strong><strong style="line&#8211;height: 1&#046;5;"> Embedded Systems Hardware:</strong></p> <ul><li><span style="line&#8211;height: 1&#046;5;">Multi&#8211;core/multi&#8211;processors systems</span></li><li><span style="line&#8211;height: 1&#046;5;">Heterogeneous embedded architectures</span></li><li><span style="line&#8211;height: 1&#046;5;">HW/SW co&#8211;design for embedded systems</span></li><li><span style="line&#8211;height: 1&#046;5;">Static and dynamic reconfigurable architectures</span></li><li><span style="line&#8211;height: 1&#046;5;">Memory hierarchies and management</span></li><li><span style="line&#8211;height: 1&#046;5;">Custom storage architectures </span><span style="line&#8211;height: 1&#046;5;">(flash, phase change memory, STT&#8211;RAM, etc&#046;)</span></li><li><span style="line&#8211;height: 1&#046;5;">Application&#8211;specific instruction&#8211;set </span><span style="line&#8211;height: 1&#046;5;">processors (ASIPs)</span></li></ul><p><strong>1&#046;3</strong><strong> Embedded Systems Software:</strong></p> <ul><li><span style="line&#8211;height: 1&#046;5;">Real&#8211;time software and operating systems</span></li><li><span style="line&#8211;height: 1&#046;5;">Middleware and virtual machines</span></li><li><span style="line&#8211;height: 1&#046;5;">Timing analysis and WCET</span></li><li><span style="line&#8211;height: 1&#046;5;">Programming models for multi&#8211;core systems</span></li><li><span style="line&#8211;height: 1&#046;5;">Profiling and compilation techniques</span></li><li><span style="line&#8211;height: 1&#046;5;">Design exploration, synthesis, validation, </span><span style="line&#8211;height: 1&#046;5;">verification, and optimization</span></li><li><span style="line&#8211;height: 1&#046;5;">HW/SW security techniques</span></li></ul><p><strong>1&#046;4 Power and Thermal Considerations in System Design:</strong></p> <ul><li><span style="line&#8211;height: 1&#046;5;">Power and thermal estimation, analysis, </span><span style="line&#8211;height: 1&#046;5;">optimization, and management techniques for </span><span style="line&#8211;height: 1&#046;5;">hardware and software systems</span></li><li><span style="line&#8211;height: 1&#046;5;">Energy&#8211; and thermal aware application mapping and scheduling</span></li><li><span style="line&#8211;height: 1&#046;5;">Energy&#8211; and thermal&#8211;aware dark silicon system design and optimization</span></li></ul><p><span class="c7"><strong>2) SYNTHESIS, VERIFICATION, AND PHYSICAL DESIGN</strong></span><br><strong>2&#046;1 High&#8211;Level, Behavioral, and Logic Synthesis and Optimization:</strong></p> <ul><li><span style="line&#8211;height: 1&#046;5;">High&#8211;level/Behavioral/Logic synthesis</span></li><li><span style="line&#8211;height: 1&#046;5;">Technology&#8211;independent optimization and technology mapping</span></li><li><span style="line&#8211;height: 1&#046;5;">Functional and logic timing ECO</span></li><li><span style="line&#8211;height: 1&#046;5;">Resource scheduling, allocation, and synthesis </span></li><li><span style="line&#8211;height: 1&#046;5;">Interaction between logic synthesis and </span><span style="line&#8211;height: 1&#046;5;">physical design</span></li></ul><p><strong>2&#046;2 Validation, Simulation, and Verification:</strong></p> <ul><li>High&#8211;level/Behavioral/Logic modeling and validation</li><li><span style="line&#8211;height: 1&#046;5;">High&#8211;level/Behavioral/Logic simulation</span></li><li><span style="line&#8211;height: 1&#046;5;">Formal, semi&#8211;formal, and assertion&#8211;based verification</span></li><li><span style="line&#8211;height: 1&#046;5;">Equivalence and property checking</span></li><li><span style="line&#8211;height: 1&#046;5;">Emulation and hardware simulation/acceleration</span></li><li><span style="line&#8211;height: 1&#046;5;">Post&#8211;silicon functional validation</span></li></ul><p><strong>2&#046;3 Cell&#8211;Library Design, Partitioning, Floorplanning, Placement:</strong></p> <ul><li><span style="line&#8211;height: 1&#046;5;">Cell&#8211;library design and optimization</span></li><li><span style="line&#8211;height: 1&#046;5;">Transistor and gate sizing</span></li><li><span style="line&#8211;height: 1&#046;5;">High&#8211;level physical design and synthesis</span></li><li><span style="line&#8211;height: 1&#046;5;">Estimation and hierarchy management</span></li><li><span style="line&#8211;height: 1&#046;5;">2D and 3D partitioning, floorplanning, and placement</span></li><li><span style="line&#8211;height: 1&#046;5;">Post&#8211;placement optimization</span></li><li><span style="line&#8211;height: 1&#046;5;">Buffer insertion and interconnect planning</span></li></ul><p><br></p> <p><span class="c7"><strong>3) CAD FOR MANUFACTURABILITY, RELIABILITY, AND TEST</strong></span><br><strong>3&#046;1 Design for Manufacturability:</strong></p> <ul><li>Process technology characterization, extraction, and modeling</li><li>CAD for design/manufacturing interfaces</li><li>CAD for reticle enhancement and lithography&#8211;related design</li><li>Variability analysis and statistical design and optimization</li><li>Yield estimation and design for yield</li></ul><p><strong>3&#046;2 Design for Reliability:</strong></p> <ul><li>Analysis and optimization for device&#8211;level reliability issues (stress, aging effects, ESD, etc&#046;)</li><li>Analysis for interconnect reliability issues (electromigration, thermal, etc)</li><li>Reliability issues related to soft errors</li><li>Design for resilience and robustness</li></ul><p><strong>3&#046;3 Testing:</strong></p> <ul><li>Digital fault modeling and simulation</li><li>Delay, current&#8211;based, low&#8211;power test</li><li>ATPG, BIST, DFT, and compression</li><li>Memory test and repair</li><li>Core, board, system, and 3D IC test</li><li>Post&#8211;silicon validation and debug</li><li>Analog, mixed&#8211;signal, and RF test</li></ul><p><span class="c7"><strong>4) CAD FOR CIRCUITS, DEVICES, AND INTERCONNECT </strong></span><br><strong>4&#046;1 Timing, Power, and Power Networks:</strong></p> <ul><li>Deterministic and statistical static timing analysis and optimization</li><li>Power and leakage analysis and optimization</li><li>Circuit and interconnect&#8211;level low power design issues</li><li>Power/ground network analysis and synthesis</li></ul><p><strong>4&#046;2 Signal Integrity and Devices/Interconnect Modeling and Simulation:</strong></p> <ul><li>Signal integrity analysis and optimization</li><li>Package modeling, analysis, and optimization</li><li>EMI/EMC simulation and optimization</li><li>Device, interconnect, and circuit modeling, extraction, and simulation</li><li>Behavioral modeling of devices and circuits</li></ul><p><strong>4&#046;3 </strong><strong>CAD for RF/analog and Multi&#8211;Domain Modeling and Analysis:</strong></p> <ul><li>CAD for analog, mixed&#8211;signal, RF</li><li>CAD for mixed&#8211;domain (semiconductor, nanoelectronic, MEMS, and electro&#8211;optical) devices, circuits, and systems</li><li>CAD for nanophotonics</li><li>Modeling and Analysis for complex dynamical systems (molecular dynamics, fluid dynamics, computational finance, etc&#046;)</li></ul><p><span class="c7"><strong>5) CAD FOR EMERGING TECHNOLOGIES AND APPLICATIONS</strong></span><br><strong>5&#046;1 Biological Systems and Bio&#8211;Electronics:</strong></p> <ul><li>CAD for biological computing systems</li><li>CAD for system and synthetic biology</li><li>CAD for bio&#8211;electronic devices, bio&#8211;sensors, MEMS, and systems</li></ul><p><strong>5&#046;2 Nanoscale and Post&#8211;CMOS Systems: </strong></p> <ul><li>New device structures and process technologies</li><li>New memory technologies (flash, phase change memory, STT&#8211;RAM, memristor, etc&#046;)</li><li>Nanotechnologies, nanowires, nanotubes, graphene, etc&#046;</li><li>Quantum computing</li><li>Optical devices and communication</li><li>CAD for bio&#8211;inspired and neuromorphic systems</li></ul><p><strong>5&#046;3 CAD for Cyberphysical Systems: </strong></p> <ul><li><span style="line&#8211;height: 1&#046;5;">CAD for display electronics</span></li><li><span style="line&#8211;height: 1&#046;5;">CAD for automotive systems and mobile electronics</span></li><li><span style="line&#8211;height: 1&#046;5;">CAD for sensor networks and Internet&#8211;of&#8211;things</span></li><li><span style="line&#8211;height: 1&#046;5;">Analysis and optimization of data centers </span></li><li><span style="line&#8211;height: 1&#046;5;">Green computing (smart grid, energy, solar panels, etc&#046;)<br></span></li></ul>