<p><span class="c7"><strong>ICCAD serves EDA and design professionals, highlighting new challenges and innovative solutions for Integrated Circuit Design Technologies and Systems. ICCAD covers the full range of CAD topics – from device and circuit–level CAD up through system–level CAD and embedded software, as well as CAD for post–CMOS design and novel application areas, such as biology and nanotechnology.</strong></span></p><p><span class="c7"><strong>1) SYSTEM–LEVEL </strong><strong>CAD</strong></span><br><strong>1</strong><strong>.1 System Design:</strong></p> <ul><li><span style="line–height: 1.5;">System–level specification, modeling, and </span><span style="line–height: 1.5;">simulation</span></li><li><span style="line–height: 1.5;">System design flows and methods</span></li><li><span style="line–height: 1.5;">HW/SW co–design, co–simulation,</span><span style="line–height: 1.5;">co–optimization, and co–exploration</span></li><li><span style="line–height: 1.5;">HW/SW platforms</span></li><li><span style="line–height: 1.5;">Rapid prototyping</span></li><li><span style="line–height: 1.5;">System design case studies and applications</span></li><li><span style="line–height: 1.5;">System–level issues for 3D integration</span></li><li><span style="line–height: 1.5;">Micro–architectural transformation</span></li><li><span style="line–height: 1.5;">Memory architecture and system synthesis</span></li><li><span style="line–height: 1.5;">System communication architecture</span></li><li><span style="line–height: 1.5;">Network–on–chip design methodologies </span><span style="line–height: 1.5;">and CAD</span></li><li><span style="line–height: 1.5;">Network–on–chip design case studies </span><span style="line–height: 1.5;">and prototyping</span></li></ul><p><strong style="line–height: 1.5;">1.2</strong><strong style="line–height: 1.5;"> Embedded Systems Hardware:</strong></p> <ul><li><span style="line–height: 1.5;">Multi–core/multi–processors systems</span></li><li><span style="line–height: 1.5;">Heterogeneous embedded architectures</span></li><li><span style="line–height: 1.5;">HW/SW co–design for embedded systems</span></li><li><span style="line–height: 1.5;">Static and dynamic reconfigurable architectures</span></li><li><span style="line–height: 1.5;">Memory hierarchies and management</span></li><li><span style="line–height: 1.5;">Custom storage architectures </span><span style="line–height: 1.5;">(flash, phase change memory, STT–RAM, etc.)</span></li><li><span style="line–height: 1.5;">Application–specific instruction–set </span><span style="line–height: 1.5;">processors (ASIPs)</span></li></ul><p><strong>1.3</strong><strong> Embedded Systems Software:</strong></p> <ul><li><span style="line–height: 1.5;">Real–time software and operating systems</span></li><li><span style="line–height: 1.5;">Middleware and virtual machines</span></li><li><span style="line–height: 1.5;">Timing analysis and WCET</span></li><li><span style="line–height: 1.5;">Programming models for multi–core systems</span></li><li><span style="line–height: 1.5;">Profiling and compilation techniques</span></li><li><span style="line–height: 1.5;">Design exploration, synthesis, validation, </span><span style="line–height: 1.5;">verification, and optimization</span></li><li><span style="line–height: 1.5;">HW/SW security techniques</span></li></ul><p><strong>1.4 Power and Thermal Considerations in System Design:</strong></p> <ul><li><span style="line–height: 1.5;">Power and thermal estimation, analysis, </span><span style="line–height: 1.5;">optimization, and management techniques for </span><span style="line–height: 1.5;">hardware and software systems</span></li><li><span style="line–height: 1.5;">Energy– and thermal aware application mapping and scheduling</span></li><li><span style="line–height: 1.5;">Energy– and thermal–aware dark silicon system design and optimization</span></li></ul><p><span class="c7"><strong>2) SYNTHESIS, VERIFICATION, AND PHYSICAL DESIGN</strong></span><br><strong>2.1 High–Level, Behavioral, and Logic Synthesis and Optimization:</strong></p> <ul><li><span style="line–height: 1.5;">High–level/Behavioral/Logic synthesis</span></li><li><span style="line–height: 1.5;">Technology–independent optimization and technology mapping</span></li><li><span style="line–height: 1.5;">Functional and logic timing ECO</span></li><li><span style="line–height: 1.5;">Resource scheduling, allocation, and synthesis </span></li><li><span style="line–height: 1.5;">Interaction between logic synthesis and </span><span style="line–height: 1.5;">physical design</span></li></ul><p><strong>2.2 Validation, Simulation, and Verification:</strong></p> <ul><li>High–level/Behavioral/Logic modeling and validation</li><li><span style="line–height: 1.5;">High–level/Behavioral/Logic simulation</span></li><li><span style="line–height: 1.5;">Formal, semi–formal, and assertion–based verification</span></li><li><span style="line–height: 1.5;">Equivalence and property checking</span></li><li><span style="line–height: 1.5;">Emulation and hardware simulation/acceleration</span></li><li><span style="line–height: 1.5;">Post–silicon functional validation</span></li></ul><p><strong>2.3 Cell–Library Design, Partitioning, Floorplanning, Placement:</strong></p> <ul><li><span style="line–height: 1.5;">Cell–library design and optimization</span></li><li><span style="line–height: 1.5;">Transistor and gate sizing</span></li><li><span style="line–height: 1.5;">High–level physical design and synthesis</span></li><li><span style="line–height: 1.5;">Estimation and hierarchy management</span></li><li><span style="line–height: 1.5;">2D and 3D partitioning, floorplanning, and placement</span></li><li><span style="line–height: 1.5;">Post–placement optimization</span></li><li><span style="line–height: 1.5;">Buffer insertion and interconnect planning</span></li></ul><p><br></p> <p><span class="c7"><strong>3) CAD FOR MANUFACTURABILITY, RELIABILITY, AND TEST</strong></span><br><strong>3.1 Design for Manufacturability:</strong></p> <ul><li>Process technology characterization, extraction, and modeling</li><li>CAD for design/manufacturing interfaces</li><li>CAD for reticle enhancement and lithography–related design</li><li>Variability analysis and statistical design and optimization</li><li>Yield estimation and design for yield</li></ul><p><strong>3.2 Design for Reliability:</strong></p> <ul><li>Analysis and optimization for device–level reliability issues (stress, aging effects, ESD, etc.)</li><li>Analysis for interconnect reliability issues (electromigration, thermal, etc)</li><li>Reliability issues related to soft errors</li><li>Design for resilience and robustness</li></ul><p><strong>3.3 Testing:</strong></p> <ul><li>Digital fault modeling and simulation</li><li>Delay, current–based, low–power test</li><li>ATPG, BIST, DFT, and compression</li><li>Memory test and repair</li><li>Core, board, system, and 3D IC test</li><li>Post–silicon validation and debug</li><li>Analog, mixed–signal, and RF test</li></ul><p><span class="c7"><strong>4) CAD FOR CIRCUITS, DEVICES, AND INTERCONNECT </strong></span><br><strong>4.1 Timing, Power, and Power Networks:</strong></p> <ul><li>Deterministic and statistical static timing analysis and optimization</li><li>Power and leakage analysis and optimization</li><li>Circuit and interconnect–level low power design issues</li><li>Power/ground network analysis and synthesis</li></ul><p><strong>4.2 Signal Integrity and Devices/Interconnect Modeling and Simulation:</strong></p> <ul><li>Signal integrity analysis and optimization</li><li>Package modeling, analysis, and optimization</li><li>EMI/EMC simulation and optimization</li><li>Device, interconnect, and circuit modeling, extraction, and simulation</li><li>Behavioral modeling of devices and circuits</li></ul><p><strong>4.3 </strong><strong>CAD for RF/analog and Multi–Domain Modeling and Analysis:</strong></p> <ul><li>CAD for analog, mixed–signal, RF</li><li>CAD for mixed–domain (semiconductor, nanoelectronic, MEMS, and electro–optical) devices, circuits, and systems</li><li>CAD for nanophotonics</li><li>Modeling and Analysis for complex dynamical systems (molecular dynamics, fluid dynamics, computational finance, etc.)</li></ul><p><span class="c7"><strong>5) CAD FOR EMERGING TECHNOLOGIES AND APPLICATIONS</strong></span><br><strong>5.1 Biological Systems and Bio–Electronics:</strong></p> <ul><li>CAD for biological computing systems</li><li>CAD for system and synthetic biology</li><li>CAD for bio–electronic devices, bio–sensors, MEMS, and systems</li></ul><p><strong>5.2 Nanoscale and Post–CMOS Systems: </strong></p> <ul><li>New device structures and process technologies</li><li>New memory technologies (flash, phase change memory, STT–RAM, memristor, etc.)</li><li>Nanotechnologies, nanowires, nanotubes, graphene, etc.</li><li>Quantum computing</li><li>Optical devices and communication</li><li>CAD for bio–inspired and neuromorphic systems</li></ul><p><strong>5.3 CAD for Cyberphysical Systems: </strong></p> <ul><li><span style="line–height: 1.5;">CAD for display electronics</span></li><li><span style="line–height: 1.5;">CAD for automotive systems and mobile electronics</span></li><li><span style="line–height: 1.5;">CAD for sensor networks and Internet–of–things</span></li><li><span style="line–height: 1.5;">Analysis and optimization of data centers </span></li><li><span style="line–height: 1.5;">Green computing (smart grid, energy, solar panels, etc.)<br></span></li></ul>
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ICCAD
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San Jose
Country
United States
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